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What you’ll be doing:
Work on a unit level testbench, working on directed and random tests and test infrastructure, and contributing to the future direction of the methodology for the testbench
Partner closely with RTL and architecture teams to help refine the microarchitecture plans to ensure that changes to the design are verifiable
Architect and plan the verification strategy and execution for sub-system features impacting your unit
Support post-silicon validation activities
What we need to see:
Currently pursuing or recently completed a BS or MS in electrical engineering or computer engineering (or equivalent experience)
Strong communication and problem solving skills
Exposure to ASIC design, ASIC verification and computer architecture,
Strong programming and debugging capability with at least one of the following languages: SystemVerilog, C and/or C++, Python and/or Perl
Deep knowledge of object-oriented programming concepts
Ways to stand out from the crowd:
Experience with testplan writing and testbench component design
Exposure to constrained random testing and coverage driven verification.
Exposure to verification methodology, like UVM
Experience with assertion-based verification, Semiformal Verification (SFV)
You will also be eligible for equity and .
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