Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field and 2 years of experience in the job offered or related occupation.
Experience and/or education must include:
Using VLSI design and timing to evaluate engineering tradeoffs.
Using knowledge of HDL to understand the functionality of the designs and suggest improvements.
Scripting in Perl and Python to automate tasks.
Using physical design concepts to improve timing, reduce congestion and to implement engineering change of orders (ECOs).
Using synthesis techniques and Boolean optimization to recover area, power and to fix setup and hold timing violations.
Using simulation and debugging tools for RTL and Netlist validation.
Using GPU architectures to understand dataflow and steer synthesis and optimizations techniques.