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Apple Graphics FE Implementation Engineer United States, Texas, Austin 89098801
23.11.2024
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Minimum Qualifications
- Experience with physical synthesis, including logic and PPA optimization techniques
- Experience with Verilog, System Verilog or other scripting languages
- Experience using logic equivalence tools for RTL and Gate-level designs
- BS + 3 years of relevant experience
Preferred Qualifications
- Understanding and application of physical design (PD) and static timing analysis (STA) principles
- Ability to analyze critical paths and guide RTL designs to optimal solutions
- Collaborate effectively with IP teams spanning multiple sites
- Familiarity with DFT insertion
- Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level
- Experience implementing ECOs for functionality and timing
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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