Broadcom Signal Integrity Lead - PCB Design 

United States, California, San Jose 

372066237

Responsibilities

• Design, optimize, simulate, and validate SERDES channels (200Gbps and beyond), including PCB segments (e.g. BGA escape, connector escape, etc).

• Create and optimize complex PCB structure models with EM field solvers (Ansys HFSS, etc) and perform post-layout extractions.

• Establish design trade-offs between package, PCB and interconnects.

• Collaborate closely with SERDES IP, Packaging, PCB teams, and suppliers.

• Evaluate PCB materials and connector solutions for next-gen designs.

• Perform VNA measurements for correlations and debug.

• Lead next-generation system feasibility studies, assessing new approaches and solutions.

• Influence industry methodology by addressing implementation constraints.

• Drive methodology improvements and automation to optimize scalable SI workflows

• Generate specifications, guidelines and system design rules for internal development and customers

AdditionalResponsibilities

• Manage multiple projects simultaneously, ensuring timely delivery and quality.

• Communicate complex technical concepts effectively in presentations, written documentation, and meetings.

• Define and document requirements for packages and PCB designs, integrating industry standards, customer needs and internal performance goals

• Provide SI models with detailed documentation for both customer and internal engineers

• Support customer analysis and debug efforts

Required Qualifications

• BS +12yrs, MS +10 yrs or PhD +7yrs Electrical Engineering or Physics and years experience

• Extensive hands-on experience in signal integrity, high speed/RF system design, and channel modeling

• Proven track record in tuning and optimizing high layer count PCB structures

• Experience with post-layout extraction

• Deep understanding of PCB fabrication techniques and their limitations

• Proficient with VNA, probing stations, spectrum analyzers, and scopes.

• Experience with Cadence Allegro tools for layout reviews.

• Strong hands-on debugging experience with SERDES channels

• Familiarity with AMI SERDES models

• Proficient in scripting and automation to optimize workflows.

• Strong foundation in digital signal processing (Desired)

• Experience with Ethernet Standards (Desired)

• EM modeling:Ansys HFSS, SIWave, Q3D, Simbeor

• Circuit simulation:Keysight ADS

• Programming/Scripting:Matlab (desired), Python, etc

• Layout Tools:Cadence APD/Allegro (desired)

Compensation and Benefits

The annual base salary range for this position is$141,000 -$225,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.