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What you’ll be doing:
Verification of the digital design, golden models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM.
Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
Responsible for understanding the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
Write and execute test plan and thoroughly verify a design in a product shipment focused / compressed schedule.
Work with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
What we need to see:
Bachelors or Masters Degree (or equivalent experience) in Electrical Engineering, Computer Science, or Computer Engineering
At least 5 years of proven experience.
Background in verification at Unit/Sub-system/SOC level and expertise in SystemVerilog a must.
Experience using random stimulus along with functional coverage and assertion-based verification methodologies a must.
Experience in verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.
Ways to stand out from the crowd:
Expertise in bus or interconnect protocols (e.g. PCI Express, USB, SATA) a big plus.
Experience in verifying complex SerDes system, understanding mixed-signal designs, and have experience in modeling of analog circuits a big plus.
Perl, Python, C/C++ programming language experience.
Good debugging and analytical skills.
Good communication skills & dream to work as a great teammate.
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