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Cisco ASIC Package Signal/Power Integrity Engineer United States, California, San Jose 129305431
27.01.2025
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The application window is expected to close on: 01/05/2025.
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Your Impact
You will work on cutting-edge FCBGA substrates that push the boundaries on power, speed, and fabrication / assembly technology. You will drive ASIC package power and signal integrity rules and layout analysis to enable on-time, high-quality manufacturing releases. You will actively implement the latest SERDES speeds and technologies while developing creative solutions for these signaling and power distribution challenges.
- Develop design rules for ultra-high speed signaling
- Analyze substrate SI/PI and provide feedback for layout
- Collaborate with the layout team to develop the best overall solution
- Collaborate with system partners to achieve the best combined power and signal integrity across the interposer, substate, and PCB.
- Document design rules and post layout extraction results
Minimum Qualifications:
- Bachelor’s degree in electrical engineering or related field
- 7+ years of experience in Signal and/or Power Integrity
- Strong background in Electromagnetics
- Good understanding of scattering and impedance network parameters
- Proficient in Ansys EM flow
- Proficient with Cadence APD for layout review
- Fluent in Keysight ADS
- Working knowledge of SPICE
Preferred Qualifications:
- Master’s degree in electrical engineering or related field
- Experience with MATLAB or Python scripting
- Experience with SI/PI of 2.5D advanced ASIC packaging
- Experience with Raptor-X
- Working knowledge of Vector Network Analysis
- Basic knowledge of IBIS
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