המקום בו המומחים והחברות הטובות ביותר נפגשים
Google Formal Verification Engineer Silicon India, Karnataka, Bengaluru 886959185
17.06.2024
Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 3 years of experience with SystemVerilog and SystemVerilog Assertion.
- Experience with formal verification.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Science, or a related field.
- Experience with scripting languages (e.g., Python/Perl, and TCL).
- Experience with formal sign-offs of industry ASIC designs.
- Knowledge of formal verification applications (e.g., sequential equivalence checking, and connectivity checking) and data-path verification.
- Knowledge of formal methodology and formal abstraction techniques.
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