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Apple CAD Design Automation Engineer Israel, Tel Aviv District 873073865
05.09.2024
Description
Developing pre-silicon RTL in SOC is a complex process; in this highly visible role, you will be responsible for creating and maintaining first class infrastructures to meet the challenges across multiple disciplines. This position tackles issues in the context of high availability, maximum efficiencies, and large design. The position will demand great flexibility in terms of problem solving and massive appetite for acquiring new knowledge.
Minimum Qualifications
- Solid programming foundation (e.g. data structure and algorithm, performance, paradigm, revision control, CI/CD, testing).
- Hands-on experience of 3+ years in Verilog and SystemVerilog
- Familiarity with VHDL a plus.
- Familiarity with registers generation/automation is a plus.
- Hands-on experience of scripting using Python or Perl, tcl is a plus.
- Experience writing or maintaining scripts or Makefile that automate RTL is a plus.
- Good communications skills are required and prior customer support experience is a plus.
- Experience in design verification or design verification automation is a plus.
- Experience in Verific APIs is a plus
Preferred Qualifications
- BSC in Electrical engineering/ Computer engineering MSC is a plus
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