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Apple Formal Verification Engineer United States, Oregon, Beaverton 831076953
27.07.2024
Description
As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP’s (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.), you will be responsible for:- Working with Apple Silicon's world-class SOC and IP design engineers to develop a formal micro-architecture specification- Developing comprehensive formal verification test plan- Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture- Crafting novel and creative solutions for verifying complex design micro-architectures- Developing and implementing re-usable and optimized formal models and verification code base- Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.
Minimum Qualifications
- A minimum of a bachelor's degree and a minimum of 3 years of relevant industry experience in silicon validation software engineering or related field.
Preferred Qualifications
- Expert in SoC, CPU, GPU, and/or Cellular designs, as well as VLSI and digital logic design and verification techniques, or expert in formal tools and methodology and their application in and industrial setting
- Detail oriented mindset and desire to overcome challenges.
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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