Required/Minimum Qualifications
- 9+ years of related technical engineering experience
- OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
- OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
- OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
- 8+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs.
- 5+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure.
- 5+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs
- 3+ years of experience with post-silicon debug
Other Requirements:
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate willbe requiredto provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred qualifications
- 12+ years technical engineering experience
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 10+ years technical engineering experience
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
- Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience.
- 6+ years of experience working on SOC integration
- 6+ years of experience with LINT/Clock Domain Crossing (CDC)/Reset Domain Crossing (RDC) closure
- 5+ years of experience with Synthesis, Timing constraints and UPF
- Experience with industry standard interfaces such as AXI, APB, JTAG
- Experience with writing System Verilog assertions
- Experience with scripting languages such as Perl or Python
- Track record of successful tapeouts in deep sub-micron technologies
- Experience with multiple post silicon bringup and validation cycles
- Excellent communication skills and the ability to facilitate collaboration across Microsoft internal groups and external vendors
- Ability and willingness to adapt and work on variety of designs
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
Microsoft will accept applications for the role until January 9, 2025.