Broadcom Asic Design Verification Engineer 

United States, California, San Jose 

755375350

You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include:

○ Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces.
○ Develop test plans and coverage metrics from specifications and write block and chip-level tests.
○ Debug RTL and Gate simulations and work with design engineers to verify fixes.
○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.
○ Replicate silicon bugs in simulation environment and validate fixes or SW workarounds.
○ Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.

○ Evaluate latest verification methodologies and develop scripts etc. to automate verification flows.
○Knowledge of mixed-signal simulations (AMS, Spice) etc.

Minimum Job Requirements:

○ Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces.
○ Develop test plans and coverage metrics from specifications and write block and chip-level tests.
○ Debug RTL and Gate simulations and work with design engineers to verify fixes.

Experience : Bachelor’s + 5+ years of related experience or Masters degree and 3+ years of related experience

Compensation and Benefits

The annual base salary range for this position is$101,000 -$162,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.