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Google ASIC Design Verification Engineer Machine Learning 
United States, California, Sunnyvale 
438311693

20.11.2024
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 2 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
  • Experience with SystemVerilog (e.g.,SystemVerilog Assertions or functional coverage).

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • 4 years of experience in design verification.
  • Experience in Power aware verification, Gate level simulations, and Post silicon bring-up.
  • Experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog for Application-Specific Integrated Circuits (ASICs).
  • Familiarity with ASIC standard interfaces and memory system architecture.