Cisco Timing Constraint Engineer 

United States, California, San Jose 

384219813

Your Impact

You are a detail-oriented Timing Constraint (SDC) Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with ASIC Front and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips. Responsibilities include:

• Developing timing constraints at block, sub-chip, and full-chip levels in multiple timing modes.
• Performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs and checking timing for unconstrained endpoints, no clock, etc.
• Resolving design and flow issues and driving execution to ensure progress and accuracy.
• At times participating in SDC validation, CDC delay check, and SDC flow development.
• Developing methodologies, guidelines, and checklists to streamline STA work, along with advising the Physical Design team on best practices.
  

Minimum Qualifications

• Bachelor’s degree in electrical or computer engineering (or other equivalent field) with 8+ years of related work experience.
• Experience with block/full chip SDC development in functional and test modes.
• Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus.
• Proficient in one or more of the following languages Perl, TCL, Python, Makefile, or other related scripting languages.

Preferred Qualifications

• Master’s Degree in electrical or computer engineering (or other equivalent field).
• Thorough understanding of Liberty file formats including standard cells/memory/IO/IP modeling and its usage in the ASIC flow.
• Prior experience with SDC debugging tools: Synopsys GCA/TCM, Cadence CCD.
• Strong communications skill and team player.

We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).