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Google Senior Logic Design Engineer Augmented Reality 
United States, California, Fremont 
30537354

01.09.2024
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 5 years of experience in logic design and verification, logic synthesis, timing closure, and static timing analysis tools.
  • Experience in Verilog or SystemVerilog HDL for RTL design, verification, and scripting languages (e.g., Python, Perl) for design automation and analysis.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with microdisplay or microLED technology.
  • Understanding of digital design fundamentals.
  • Familiarity with low-power design techniques.