Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience in logic design and verification, logic synthesis, timing closure, and static timing analysis tools.
Experience in Verilog or SystemVerilog HDL for RTL design, verification, and scripting languages (e.g., Python, Perl) for design automation and analysis.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with microdisplay or microLED technology.