Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with SystemVerilog, Design Verification Test, Universal Verification Methodology. 3...
תיאור: Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience with SystemVerilog, Design Verification Test, Universal Verification Methodology.
- 3 years of experience working with test methodologies, creating test plans, and writing test cases.
Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in low-power design verification.