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Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs
Define, develop, and automate flows and methodologies to efficiently build, deliver, and support a system-level IP
Deliver IP and support projects by applying the performance monitoring system
Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency, and more)
Design and implement RTL features (microarchitecture and RTL)
Work with architects, designers, and software engineers to accomplish your tasks
BS or equivalent experience in Electrical Engineering, Computer Engineer, or related degree required, advanced degrees (MS, PhD) a plus
3+ years of relevant industry experience and strong coding skills in Perl/Python or other industry-standard scripting languages
Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chipdesign/implementationflow, and design automation
Good understanding of SOC architecture, including CDC, multiple-power domains, performance analysis, latency, and data flow
Excellent debugging and analytical skills
Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB)
Great communication and collaboration skills to interact within the team and with cross-functional teams
Hands on experience in object-oriented programming
Prior design on system level IP (Clocks/DFT/Resets)
Experience developing methodologies used by others
Hands- on silicon debug is a plus.
Exposure to physical design
You will also be eligible for equity and .
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What you'll be doing:
Develop and deploy in-house tools and workflows to support engineering business units across NVIDIA.
Take ownership of tools that verify common design blocks used in all products at NVIDIA.
Act as a "DevOps" engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users.
Build new workflows and methodologies to ensure smooth integration into various IP development environments.
What we need to see:
Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering (or equivalent experience).
3+years of proven experience preferred.
Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.
Proficiency in scripting using modern Python and/or Perl.
Experience with Unix/Linux shell scripting and Makefiles.
Strong ability to collaborate with multi-functional teams and effectively communicate technical details.
Ways to stand out from the crowd:
Prior experience in ASIC verification.
Knowledge of Clocks/Resets design and verification.
Exposure to CDC related design/verification flows.
Exposure to backend flows (Synthesis, Timing, etc).
You will also be eligible for equity and .
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What you'll be doing:
Work with architects, designers, and performance engineers to develop an energy-efficient GPU.
Identify key design features and workloads for building Machine Learning based unit power/energy models.
Develop and own methodologies and workflows to train models using ML and/or statistical techniques.
Improve the accuracy of trained models by using different model representations, objective functions, and learning algorithms.
Develop methodologies to estimate data movement power/energy accurately.
Correlate the predicted energy from models built at different stages of the design cycle, with the goal of bridging early estimates to silicon.
Work with performance infrastructure teams to integrate power/energy models into their platforms to enable combined reporting of performance and power for various workloads.
Develop tools to debug energy inefficiencies observed in various workloads run on silicon, RTL, and architectural simulators. Identify and suggest solutions to fix the energy inefficiencies.
Prototype new architectural features, build an energy model for those new features, and analyze the system impact.
Identify, suggest, and/or participate in studies for improving GPU perf/watt.
What we need to see:
Pursuing or recently completed a MS or PhD in Electrical Engineering, Computer Engineering, Computer Scienceor equivalent experience.
Strong coding skills, preferably in Python, C++.
Background in machine learning, AI, and/or statistical modeling.
Background in computer architecture and interest in energy-efficient GPU designs.
Familiarity with Verilog and ASIC design principles is a plus.
Ability to formulate and analyze algorithms, and comment on their runtime and memory complexities.
Basic understanding of fundamental concepts of energy consumption, estimation, and low power design.
Desire to bring quantitative decision-making and analytics to improve the energy efficiency of our products.
Good verbal/written communication and interpersonal skills.
You will also be eligible for equity and .
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What you’ll be doing:
Be a technical specialist on GPU and networking products directly supporting sales account managers, working closely with the team to secure design wins.
Actively establish the technical relationship with our customer’s engineers, management, and architects at focus accounts.
Identify customer architectures and key product requirements in the CSP/OEM AI market.
Provide onsite support to solve problems in hardware and software, and deep learning inference.
Lead the support of the product through the design-in phase all the way to the product end of life.
Create technical solutions such as hardware & software demos and example system designs.
Provide technical and sales training to the direct sales team and channel partners.
Establish strong relationships and communication channels with internal teams.
What we need to see:
BS or MS in Engineering, Electrical Engineering, Physics, or Computer Science (or equivalent experience).
8+ years of work-related experience in the high-tech electronics industry in a system design role or technical customer support role.
Capable of working in a constantly evolving environment without losing focus.
Ability to multitask effectively in a dynamic environment.
Expert analytical and problem-solving skills.
Strong time-management and organization skills for coordinating multiple initiatives, priorities, and implementations of new technology and products into very complex projects.
Strong written and oral communication skills in English with the ability to effectively collaborate with management and engineering.
Ways to stand out from the crowd:
ARM and NVIDIA GPU development
Hands-on troubleshooting of Ethernet physical layer issues, including signal integrity and link training failures.
Embedded Linux System, APIs and similar embedded OS knowledge.
Experience working with OEMs in the industrial, military, and ruggedized computing space.
CPU and PCIe Architecture knowledge
You will also be eligible for equity and .
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What you'll be doing:
Develop test plans, tests and verification infrastructure for verifying global IP across multiple products
Define, develop, and automate flows and methodologies to efficiently build, deploy, and verify generated RTL
Ensure code and functional coverage of all the RTL which you will verify
Build verification components using SV/UVM methodology
Driving coverage-based verification closure
Collaborate with design teams across NVIDIA to find corner cases and resolve verification related issues
What we need to see:
BS/MS in Electrical or Computer Engineering (or equivalent experience)
5+ years of proven design verification experience
Experience in pre-silicon verification (UVM, SystemVerilog), ASICdesign/implementationflow, and design automation
Programming and scripting experience in Perl or Python
Excellent debugging and analytical skills
Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB)
Strong communication and collaboration skills to interact within the team and across functional teams
Ways to stand out from the crowd:
Previous experience automating tasks in the design verification process
Hands on experience in object-oriented programming
Prior design or verification experience at the IP or block level
Experience developing methodologies used by others
Demonstrated ability to drive a project to completion
You will also be eligible for equity and .
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Based in Austin, Texas, the Senior Facilities Workplace Services Manager will be responsible for co-managing the Americas portfolio with a peer and be responsible for the leadership and execution of all aspects of the Facilities Workplace Service Organization including all soft services, moves, adds and changes program, janitorial services, landscaping, corporate event services, and reception services. Reporting to the Senior Director of Facilities Operations, the Senior Workplace Manager will have additional responsibilities, including management of special projects in support of the design, planning and project teams.
What you'll be doing:
Build, mentor, and develop a team of office managers/vendor partners and their teams to execute operations, strengthen leadership, and assist in achieving career growth, aligned with our core values.
Provide strategic input for all Facility Services and Amenities across region. Develop program delivery standards and guidelines focusing on Employee Experience and drive for consistency and best in class practices.
Conduct and certify Quarterly Business Reviews for key vendors, including review of Service Level Agreements, and Key Performance Measurements.
Maintaining Facilities in Region in compliance with local, county, state, and federal regulations.
Assure capital projects, operations projects and re-configurations are managed by facilities teams focused on customer experience.
Ensure scopes of services are met by conducting planned inspections to confirm levels of service and standards are met.
Develop and maintain positive relationships with vendors and suppliers to ensure the delivery of high quality services.
Partner with leadership and key collaborators including Site Leader, HR, IT, EH&S, Planning and Security to build and sustain an outstanding employee experience and workplace environment.
What we need to see:
10+ overall years of experience in a similar role within a complex multinational corporate environment. Experience within a dynamic and fast-moving technology organization is strongly preferred.
5+ years of leadership experience in developing and building employee engagement including mentoring and coaching of employees.
Bachelor’s degree or equivalent experience, preferably in Engineering, Architecture, or related field.
Experience in facilities services management, vendor management, and contract negotiation, within a global organization.
Strong customer service, presentation skills, and excellent written and verbal interpersonal skills.
You are experienced with handling budgets (including capital budget justification) with financial and contract management experience.
Experience with analyzing reports, metrics, and trends.
You have expertise in facilities project management, design and construction, including industry practices, forms of contract, risk management and quality assurance.
Possess an understanding of building MEP systems, labs, data center, and office spaces, with additional understanding of process piping systems including chilled water, PCW, CDA.
Ability to solve complex problems by taking a broad perspective to identify solutions as well as a strong process and procedural background in a high technology company required to support the business goals.
General knowledge of building, fire, mechanical, electrical, and plumbing codes and OSHA and regulatory requirements.
You will also be eligible for equity and .
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What you'll be doing:
Design and maintain the unit level/sub-system Verification environment.
Understand the architecture specifications, develop and carry out the test plan to verify the design.
Create UVM components, sequences, tests and scoreboards.
Sign off on the verification efforts with very high-quality code and functional coverage.
Launch regressions, resolve the issues, and make forward progress towards achieving the DV milestone targets
Automate the manual steps involved in launching build, regression, and triage.
Collaborate with architects, designers, and software engineers to achieve project goals.
Proactively contributes to improving the efficiency of the testbenches by embracing the latest techniques.
Responsible for end-to-end verification of IPs, ensuring the highest quality delivery.
What we need to see:
Bachelor’s or Master’s degree in Computer or Electrical Engineering (or equivalent experience) with 3 years of relevant experience.
Proficient with System Verilog, UVM required and OOPS based programming.
Strong coding skills in Python or other industry-standard scripting languages.
Strong understanding of RTL design (Verilog).
Good understanding of computer architecture fundamentals.
Familiarity with verification tools such as VCS or equivalent simulation tools, and debug tools like Verdi.
You will also be eligible for equity and .
These jobs might be a good fit

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Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs
Define, develop, and automate flows and methodologies to efficiently build, deliver, and support a system-level IP
Deliver IP and support projects by applying the performance monitoring system
Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency, and more)
Design and implement RTL features (microarchitecture and RTL)
Work with architects, designers, and software engineers to accomplish your tasks
BS or equivalent experience in Electrical Engineering, Computer Engineer, or related degree required, advanced degrees (MS, PhD) a plus
3+ years of relevant industry experience and strong coding skills in Perl/Python or other industry-standard scripting languages
Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chipdesign/implementationflow, and design automation
Good understanding of SOC architecture, including CDC, multiple-power domains, performance analysis, latency, and data flow
Excellent debugging and analytical skills
Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB)
Great communication and collaboration skills to interact within the team and with cross-functional teams
Hands on experience in object-oriented programming
Prior design on system level IP (Clocks/DFT/Resets)
Experience developing methodologies used by others
Hands- on silicon debug is a plus.
Exposure to physical design
You will also be eligible for equity and .
These jobs might be a good fit