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Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs
Define, develop, and automate flows and methodologies to efficiently build, deliver, and support a system-level IP
Deliver IP and support projects by applying the performance monitoring system
Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency, and more)
Design and implement RTL features (microarchitecture and RTL)
Work with architects, designers, and software engineers to accomplish your tasks
BS or equivalent experience in Electrical Engineering, Computer Engineer, or related degree required, advanced degrees (MS, PhD) a plus
3+ years of relevant industry experience and strong coding skills in Perl/Python or other industry-standard scripting languages
Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chipdesign/implementationflow, and design automation
Good understanding of SOC architecture, including CDC, multiple-power domains, performance analysis, latency, and data flow
Excellent debugging and analytical skills
Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB)
Great communication and collaboration skills to interact within the team and with cross-functional teams
Hands on experience in object-oriented programming
Prior design on system level IP (Clocks/DFT/Resets)
Experience developing methodologies used by others
Hands- on silicon debug is a plus.
Exposure to physical design
You will also be eligible for equity and .
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