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Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering system-level IP to measure performance across multiple projects.
What you'll be doing:
Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs
Define, develop, and automate flows and methodologies to efficiently build, deliver, and support a system-level IP
Deliver IP and support projects by applying the performance monitoring system
Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency, and more)
Design and implement RTL features (microarchitecture and RTL)
Work with architects, designers, and software engineers to accomplish your tasks
What we need to see:
MS (or equivalent experience) in Electrical or Computer Engineering with 2 to 8 years of RTL Design experience, or BS with 4 to 10 years of RTL Design experience.
Strong coding skills in Perl/Python or other industry-standard scripting languages
Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chipdesign/implementation flow,and design automation
Good understanding of SOC architecture, including CDC, multiple-power domains, performance analysis, latency, and data flow.
Excellent debugging and analytical skills
Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB)
Great communication and collaboration skills to interact within the team and with cross-functional teams
You will also be eligible for equity and .
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