Asic Design Engineer Hardware Tools Methodology Development jobs at Nvidia in United States, Austin

• Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs

• Define, develop, and automate flows and methodologies to efficiently build, deliver, and support a system-level IP

• Deliver IP and support projects by applying the performance monitoring system

• Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency, and more)

• Design and implement RTL features (microarchitecture and RTL)

• Work with architects, designers, and software engineers to accomplish your tasks

• BS or equivalent experience in Electrical Engineering, Computer Engineer, or related degree required, advanced degrees (MS, PhD) a plus

• 3+ years of relevant industry experience and strong coding skills in Perl/Python or other industry-standard scripting languages

• Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chipdesign/implementationflow, and design automation

• Good understanding of SOC architecture, including CDC, multiple-power domains, performance analysis, latency, and data flow

• Excellent debugging and analytical skills

• Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB)

• Great communication and collaboration skills to interact within the team and with cross-functional teams

• Hands on experience in object-oriented programming

• Prior design on system level IP (Clocks/DFT/Resets)

• Experience developing methodologies used by others

• Hands- on silicon debug is a plus.

• Exposure to physical design

What you'll be doing:

• Develop and deploy in-house tools and workflows to support engineering business units across NVIDIA.

• Take ownership of tools that verify common design blocks used in all products at NVIDIA.

• Act as a "DevOps" engineer for automated RTL generation by developing new features and maintaining efficient operations for existing users.

• Build new workflows and methodologies to ensure smooth integration into various IP development environments.
  

What we need to see:

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering (or equivalent experience).

• 3+years of proven experience preferred.

• Solid understanding of fundamental digital design concepts with hands-on experience in Verilog.

• Proficiency in scripting using modern Python and/or Perl.

• Experience with Unix/Linux shell scripting and Makefiles.

• Strong ability to collaborate with multi-functional teams and effectively communicate technical details.

Ways to stand out from the crowd:

• Prior experience in ASIC verification.

• Knowledge of Clocks/Resets design and verification.

• Exposure to CDC related design/verification flows.

• Exposure to backend flows (Synthesis, Timing, etc).

What you'll be doing:

• Work with architects, designers, and performance engineers to develop an energy-efficient GPU.

• Identify key design features and workloads for building Machine Learning based unit power/energy models.

• Develop and own methodologies and workflows to train models using ML and/or statistical techniques.

• Improve the accuracy of trained models by using different model representations, objective functions, and learning algorithms.

• Develop methodologies to estimate data movement power/energy accurately.

• Correlate the predicted energy from models built at different stages of the design cycle, with the goal of bridging early estimates to silicon.

• Work with performance infrastructure teams to integrate power/energy models into their platforms to enable combined reporting of performance and power for various workloads.

• Develop tools to debug energy inefficiencies observed in various workloads run on silicon, RTL, and architectural simulators. Identify and suggest solutions to fix the energy inefficiencies.

• Prototype new architectural features, build an energy model for those new features, and analyze the system impact.

• Identify, suggest, and/or participate in studies for improving GPU perf/watt.

What we need to see:

• Pursuing or recently completed a MS or PhD in Electrical Engineering, Computer Engineering, Computer Scienceor equivalent experience.

• Strong coding skills, preferably in Python, C++.

• Background in machine learning, AI, and/or statistical modeling.

• Background in computer architecture and interest in energy-efficient GPU designs.

• Familiarity with Verilog and ASIC design principles is a plus.

• Ability to formulate and analyze algorithms, and comment on their runtime and memory complexities.

• Basic understanding of fundamental concepts of energy consumption, estimation, and low power design.

• Desire to bring quantitative decision-making and analytics to improve the energy efficiency of our products.

• Good verbal/written communication and interpersonal skills.

What you'll be doing:

• Develop test plans, tests and verification infrastructure for verifying global IP across multiple products

• Define, develop, and automate flows and methodologies to efficiently build, deploy, and verify generated RTL

• Ensure code and functional coverage of all the RTL which you will verify

• Build verification components using SV/UVM methodology

• Driving coverage-based verification closure

• Collaborate with design teams across NVIDIA to find corner cases and resolve verification related issues
  

What we need to see:

• BS/MS in Electrical or Computer Engineering (or equivalent experience)

• 5+ years of proven design verification experience

• Experience in pre-silicon verification (UVM, SystemVerilog), ASICdesign/implementationflow, and design automation

• Programming and scripting experience in Perl or Python

• Excellent debugging and analytical skills

• Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB)

• Strong communication and collaboration skills to interact within the team and across functional teams

Ways to stand out from the crowd:

• Previous experience automating tasks in the design verification process

• Hands on experience in object-oriented programming

• Prior design or verification experience at the IP or block level

• Experience developing methodologies used by others

• Demonstrated ability to drive a project to completion

What you'll be doing:

• Design and maintain the unit level/sub-system Verification environment.

• Understand the architecture specifications, develop and carry out the test plan to verify the design.

• Create UVM components, sequences, tests and scoreboards.

• Sign off on the verification efforts with very high-quality code and functional coverage.

• Launch regressions, resolve the issues, and make forward progress towards achieving the DV milestone targets

• Automate the manual steps involved in launching build, regression, and triage.

• Collaborate with architects, designers, and software engineers to achieve project goals.

• Proactively contributes to improving the efficiency of the testbenches by embracing the latest techniques.

• Responsible for end-to-end verification of IPs, ensuring the highest quality delivery.

What we need to see:

• Bachelor’s or Master’s degree in Computer or Electrical Engineering (or equivalent experience) with 3 years of relevant experience.

• Proficient with System Verilog, UVM required and OOPS based programming.

• Strong coding skills in Python or other industry-standard scripting languages.

• Strong understanding of RTL design (Verilog).

• Good understanding of computer architecture fundamentals.

• Familiarity with verification tools such as VCS or equivalent simulation tools, and debug tools like Verdi.

What you'll be doing:

• Design and maintain the unit level/sub-system Verification environment.

• Understand the architecture specifications, develop and carry out the test plan to verify the design.

• Create the UVM components, sequences, tests and scoreboards.

• Sign off on the verification efforts with very high quality code and functional coverage.

• Launch regressions, resolve the issues, and make forward progress towards achieving the DV milestone targets

• Automate the manual steps involved in launching build, regression, and triages.

• Collaborate with architects, designers, and software engineers to achieve the project goals.

• Pro-actively contribute to improving the efficiency of the testbenches by embracing the latest techniques.

What we need to see:

• Completing an MS or higher in Computer or Electrical Engineering (or equivalent experience).

• Experience in System Verilog, UVM and in general OOPS based programming.

• Strong coding skills in Python or other industry-standard scripting languages.

• Strong understanding of RTL design (Verilog).

• Good understanding of computer architecture fundamentals.

• Familiarity with verification tools such as VCS or equivalent simulation tools, and debug tools like Verdi.

Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering system-level IP to measure performance across multiple projects.

What you'll be doing:

• Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs.

• Learn and contribute to the development and automation of flows and methodologies to efficiently build, deliver, and support a system-level IP.

• Support projects by applying the performance monitoring system under the guidance of senior engineers.

• Learn and run RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency, and more).

• Design and implement RTL features (microarchitecture and RTL) with mentorship from experienced engineers.

• Work with architects, designers, and software engineers to accomplish your tasks.

What we need to see:

• Completing a Master's degree (or equivalent experience) in Electrical or Computer Engineering, or a Bachelor's degree with 6+ months of relevant experience.

• Strong academic background in digital design and computer architecture.

• Programming experience in Python or other scripting languages.

• Knowledge of RTL design (Verilog) and digital design concepts.

• Understanding of basic SOC architecture concepts.

• Excellent problem-solving and analytical skills.

• Proven teamwork and communication across multiple teams.