Senior Staff Hardware Design Engineer jobs at Marvell
Marvell Senior Demand Planner United States, California
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Marvell Analog IC Design Engineer Senior Staff United States, California, Irvine
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What You Can Expect
- Understand the requirements of the product and how your block fits into it.
- Capture schematics in Cadence Virtuoso
- Investigate new architectures to come up with the best choice for the requirements.
- Perform layout of an integrated circuit block.
- Create an extracted model of the design.
- Run simulations to verify the performance of the design.
- Document the design and hold a design review with the design team.
What We're Looking For
Looking to fill a 4 to 8 month position with a flexible start date.
- Candidate MUST be currently pursuing a MSc or PhD degree in EE or related technical field(s)
- Detailed understanding of various different circuit blocks such as:
- Opamps, VGAs, High Speed Drivers, TIAs, Mixers, VCOs.
- Ability to analyze feedback networks.
- Familiarity with layout.
- Understanding of device physics.
- Strong communication, presentation, and documentation skills
- Knowledge of Cadence design software.
- Knowledge of SiGe Bipolar as well as CMOS is a plus.
- Ability to perform electro-magnetic analysis and simulation of planar inductors, trasmission lines and t-coils.
- 0-4 years of previous industry experience
Marvell Analog IC Design Principal Engineer United States, California
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What You Can Expect
You will be working with multi-functional teams to deliver high-speed transceiver products. You will define specifications based on link budget, behavioral modeling, and transistor-level feasibility. You will also drive schematic design and collaborate on mask design for implementation. And finally, with the team, you will drive designs into volume production and delight customers.
What We're Looking For
- Bachelor's degree in Electrical Engineering or related fields and 5-10 years of related professional experience.
- Master’s degree and/or PhD in Electrical Engineering or related fields and 3-5 years of experience.
- The ideal candidate will have a deep understanding of analog mixed-signal design with experience in high-speed transceivers.
- Solid understanding and experience of designing analog mixed-signal circuit blocks including PLL, phase interpolator, low jitter clock distribution, bandgap, biasing circuits, LDO regulators, amplifiers, comparators, high-speed DACs and ADCs, filters.
- In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques.
- Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization.
EXPERIENCE IN THE FOLLOWING AREAS IS DESIRABLE:
- Experience in lab testing of high-speed transceivers .
- Modeling of passive on-chip elements such as inductor, T-coil, and transformer.
- Able to build VerilogA/AMS behavioral models.
- Able to analyze and lead characterization data from lab and volume testing
- Knowledge of ESD requirements.
Expected Base Pay Range (USD)
140,350 - 210,200, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
Marvell Senior Staff Verification Engineer United States, Massachusetts
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What You Can Expect
Develop photonics IC (PIC) and electronics IC (EIC) co-design flow.
Define PIC and EIC IO pad frame and 2.5D interposer floor plan.
Lead PIC and EIC interconnect schematic and layout design process.
Define PIC and EIC hybrid integration packaging design rules, process flow, and material sets.
Lead optical package development to establish package manufacturability and reliability.
Collaborate with cross-functional teams consisting of Digital and Analog Circuit designers, Signal/Power Integrity, and substrate layout, and system design team.
Drive optical product package qualification activities from initial concept to production.
What We're Looking For
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5+ years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3+ years of experience,
Expertise in designing hybrid multi-chip integration using 2.5D/3D packaging. Direct experience in Si Photonics based packaging design is a plus.Experience in layout desig tools for ICs and or packaging, and 2.5D/3D EM simulation tools such as HFSS, SI-Wave, Momentum, IE3D, CST, PowerSI.
Device or package characterization and testing as required in the developmentenvironment. Highspeed testing background is preferred.
A strong understanding of wafer level packaging process flow.
Direct experience in collaborating with major OSAT for developing advanced packaging technology for high-speed optics and/or electronics IC is a plus.
Ability to work with a large body of data and the necessary statistical analysis tools, and the ability to present the data and ideas to a diverse audience.
Effective communication and presentation
Team player. Expected to work with cross-functional team.
Marvell Principal Applications Engineer United States, California
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What You Can Expect
In this role you will lead development of hardware platforms for integrated optical transceiver engines for high speed fiber optic communications applications. This role requires expertise in schematic entry, communications, hardware protocols, printed circuit board fabrication and design, and analog / RF signaling. This role will also use high speed test equipment such as VNA or PNA or high speed oscilloscopes. The candidate will also collaborate with operations, product engineering, test engineering, applications engineering and Business Development teams to support hardware development. This role is on-site.
- Lead the design and development of hardware including DUT cards, interposers, socket designs, and handler boards for complex semiconductor devices.
- Own schematic capture, layout reviews, stack-up optimization, and BOM management for substrates and printed circuit boards.
- Review power integrity (PI) and signal integrity (SI) simulations to ensure compliance with electrical specifications.
- Collaborate with cross-functional teams across time zones to define hardware requirements and integrate new product features.
- Drive component selection, considering performance, availability, and cost.
- Develop and maintain automation scripts in Python, C++, and MATLAB to streamline validation and correlation processes.
- Interface with manufacturing teams to support DFMA and ensure smooth transition to production.
- Author technical documentation and contribute to internal publications and reports
What We're Looking For
- Master’s degree in Electrical or Electronic Engineering with 3+ years of experience, or Bachelor’s degree with 5+ years of relevant experience.
- Proven expertise in hardware design for semiconductor testing or power delivery systems.
- Strong background in PI/SI analysis using tools such as PowerDC, PowerSI, ADS, HFSS, and Clarity 3D.
- Experience with schematic and layout tools such as Cadence Virtuoso.
- Familiarity with communication protocols including SPI, I2C, I3C, SPMI, and UART.
- Hands-on experience with lab instruments: oscilloscopes, VNAs, signal generators, and electronic loads.
- Excellent problem-solving skills and ability to manage multiple priorities in a fast-paced environment.
- Strong communication skills and ability to work effectively in cross-functional, global teams.
- Demonstrated ability to publish and present technical work is a plus.
Expected Base Pay Range (USD)
130,740 - 195,800, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
Marvell Senior Staff Engineer Physical Design United States, California
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What Can You Expect
Physical Design Execution: Perform synthesis, floor planning, place and route, clock tree synthesis, and timing analysis on complex blocks. You will ensure that designs meet performance, power, and area goals across advanced technology nodes like 7nm, 5nm and 3nm.
Methodology Development: Work on Place and Route methodology for efficient and robust design processes, enhancing Marvell’s physical design flow. You will be tasked with maintaining and supporting these methodologies to ensure continued improvements in efficiency and accuracy.
Timing and Logic ECOs: Develop and implement timing and logic Engineering Change Orders (ECOs) while closely collaborating with RTL teams to address congestion and timing issues.
Cross-functional Collaboration: Work closely with the frontend design and global timing teams to resolve block-level timing issues, ensuring a smooth tape-out process.
Innovative Challenges: Tackle complex, multi-disciplinary challenges and play a key role in driving technology advancements in automotive, 5G/6G, networking, and server chip designs. Your role is a critical interface between backend design, frontend design, and methodology teams.
What We're Looking For
Educational Background: Bachelor’s degree in Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Electrical Engineering or related fields with 3-5 years of experience. Coursework and projects must include digital logic design, circuit testing, and timing analysis.
Professional Experience: At least 5 years of related experience in physical design, with a proven track record of successful tape-outs, preferably top-level implementation. Experience with advanced technology nodes such as 7nm, 5nm, or below is highly desirable. Experience with chiplet-based architectures and full-chip physical design a plus. Strong experience in static timing analysis (STA), with a focus on timing closure and signoff using PrimeTime is highly desirable.
Hands-On Expertise: Strong experience with industry-standard EDA tools, including synthesis, floor planning, place and route, clock tree synthesis, timing closure, and physical verification.
Physical Design Methodologies: Proven experience working with RTL-to-GDS flows, including experience with digital logic and computer architecture using Verilog/VHDL. Familiarity with timing analysis and congestion resolution is crucial.
Scripting Skills: Demonstrable proficiency in scripting languages such as Perl, tcl, and Python for automation and workflow enhancement.
Communication & Teamwork: Excellent communication skills and a proven ability to work effectively in a collaborative, team-oriented environment.
Problem-Solving: Ability to troubleshoot and resolve complex timing and physical design issues at block and partition levels.
Expected Base Pay Range (USD)
124,420 - 186,400, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
Marvell Analog Layout Senior Staff Engineer United States, California
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Our innovative approaches have resulted in the company’s products being first to market in many of key areas, including opto-electronics and DSP based transceivers providing most advanced chips and subsystems solutions to address todays and future multi-100Gig interconnect requirements for the ever-increasing demand of higher data rates.
What You Can Expect
As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing highly sophisticated CMOS transceiver/SERDES products.Responsibilitieswould include implementation and verification of circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as Spectre, MATLAB etc.
What We're Looking For
- Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5+ years of experience.
To succeed in this role, you must have the following:
Hands-on experience in designing mixed signal circuits including ADCs, DACs, RX, TX, PLLs, Filters, Bandgap bias circuits, regulators, and other analog circuits.
Specialized depth and/or breadth of expertise.
Ability to apply innovative solutions to resolve complex issues.
History of identifying and developing best practices that deliver high-quality and effective solutions.
Strong knowledge on the deep sub-micron CMOS technologies.
Knowledge and experience on low power and high speed design techniques.
Excellent problem solving and analytical skills.
Strong knowledge on IC design CAD tools such as Spectre, Spice, Matlab, Hsim, Verilog, etc.
Lab testing skills to evaluate the prototype unit to the design specification.
Expected Base Pay Range (USD)
141,900 - 210,010, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
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