Marvell Senior Demand Planner 

United States, California 

217649512

Job Responsibilities: · SOC, Sub system & Block verification activities - should have participated in successful completion of SOC/Subsys projects across all phases from SOC/Subsys Specification to Silicon. · Responsible for complete SOC/Subsys/Block verification activities like - develop verification architecture and verification plan, develop UVM based testbench, Integrate in-house verification components + complex VIP’s ( ARM, Cadence, Synopsys, etc), develop test cases (UVM & assembly), verify and do coverage analysis in RTL and gate level design. · Conduct reviews in all the SOC/Subsys verification phases, to achieve desired quality + on-schedule deliverables and drive SOC/Subsys verification process improvement. · Mentor junior engineers and technically guide and monitor them on their day to day technical tasks. · Work effectively with a global team and be self-motivated to manage deliverables · Communicate clearly both verbally and in writing.

Technical Requirement’s: · Bachelor’s degree in CS/EE with 14–18 years of relevant experience, or Master degree in CS/EE with 12–16 years of relevant experience · Must Lead a team of 4-6 engineers · Experience in SOC/Subsys level/Block verification of ARM-based SOCs; experience in ARM based boot environment preferred. · Knowledgeable of ARM architecture and AMBA bus standards like AXI-4, CHI and ACE. · Experience with industry standard interfaces such as DDR, eMMC, PCIE, Ethernet and USB. · Experience in coding UVM SOC/Subsys level testbenches, BFM, scoreboards, monitors, etc. · Proficient in writing and debugging tests in UVM as well as C. · Exposure to Cadence, Synopsys, Mentor and/or ARM verification tools. · Experience with assertion-based formal verification tools. · Proficient in programming in scripting languages such as tcl and Perl. · Understanding of hardware emulation support. · Familiarity with TLMs in SystemC. · Experience in Version tools like CVS, SVN, GIT etc.