Marvell Senior Staff Engineer Physical Design United States, California 933019349
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What Can You Expect
Physical Design Execution: Perform synthesis, floor planning, place and route, clock tree synthesis, and timing analysis on complex blocks. You will ensure that designs meet performance, power, and area goals across advanced technology nodes like 7nm, 5nm and 3nm.
Methodology Development: Work on Place and Route methodology for efficient and robust design processes, enhancing Marvell’s physical design flow. You will be tasked with maintaining and supporting these methodologies to ensure continued improvements in efficiency and accuracy.
Timing and Logic ECOs: Develop and implement timing and logic Engineering Change Orders (ECOs) while closely collaborating with RTL teams to address congestion and timing issues.
Cross-functional Collaboration: Work closely with the frontend design and global timing teams to resolve block-level timing issues, ensuring a smooth tape-out process.
Innovative Challenges: Tackle complex, multi-disciplinary challenges and play a key role in driving technology advancements in automotive, 5G/6G, networking, and server chip designs. Your role is a critical interface between backend design, frontend design, and methodology teams.
What We're Looking For
Educational Background: Bachelor’s degree in Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Electrical Engineering or related fields with 3-5 years of experience. Coursework and projects must include digital logic design, circuit testing, and timing analysis.
Professional Experience: At least 5 years of related experience in physical design, with a proven track record of successful tape-outs, preferably top-level implementation. Experience with advanced technology nodes such as 7nm, 5nm, or below is highly desirable. Experience with chiplet-based architectures and full-chip physical design a plus. Strong experience in static timing analysis (STA), with a focus on timing closure and signoff using PrimeTime is highly desirable.
Hands-On Expertise: Strong experience with industry-standard EDA tools, including synthesis, floor planning, place and route, clock tree synthesis, timing closure, and physical verification.
Physical Design Methodologies: Proven experience working with RTL-to-GDS flows, including experience with digital logic and computer architecture using Verilog/VHDL. Familiarity with timing analysis and congestion resolution is crucial.
Scripting Skills: Demonstrable proficiency in scripting languages such as Perl, tcl, and Python for automation and workflow enhancement.
Communication & Teamwork: Excellent communication skills and a proven ability to work effectively in a collaborative, team-oriented environment.
Problem-Solving: Ability to troubleshoot and resolve complex timing and physical design issues at block and partition levels.
Expected Base Pay Range (USD)
124,420 - 186,400, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
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