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Test Engineer Intern - Bachelors jobs at Marvell in Taiwan, Hsinchu

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Taiwan
Hsinchu
5 jobs found
04.09.2025
M

Marvell Principal Engineer Design Verification Taiwan, Hsinchu

Limitless High-tech career opportunities - Expoint
Design, implement, and maintain large-scale HPC clusters for EDA workloads, ensuring high availability, fault tolerance, and efficient resource utilization. Manage, configure, and optimize LSF job scheduling systems to support diverse...
Description:
As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to participate in defining the whole organization's design infrastructure, methodology and workflows.


What You Can Expect

  • Design, implement, and maintain large-scale HPC clusters for EDA workloads, ensuring high availability, fault tolerance, and efficient resource utilization.
  • Manage, configure, and optimize LSF job scheduling systems to support diverse verification workflows.
  • Develop, automate, and monitor deployment, configuration, and operational processes for EDAinfrastructure.
  • Collaborate with EDA engineers and designers to refine verification flows to run optimally on the grid.
  • Implement and advance CI/CD pipelines to streamline the deployment, testing, and monitoring of infrastructure and EDA flows.
  • Provide troubleshooting and support for users and the infrastructure.
  • Monitor infrastructure health, performance, and usage; proactively identify, resolve, and document issues.
  • Ensure compliance with security bestpractices, licensemanagement, and data protection requirements.
  • Contribute to architectural innovation and process improvement for future scalability and efficiency.
  • Participate in incident management teams for prompt issue resolution.

What We're Looking For

  • Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field.

Proficiency with Programming or scripting in languages such as Python, Bash, or Perl for automation and workflow development.

  • Working knowledge of Linux system administration and cluster troubleshooting.

Familiarity withinfrastructure-as-code,configuration management, and monitoring , DevOps; SRE concepts; CI/CD and GitOps.

  • Strong communication and collaboration skills; ability to work in cross-functional teams.
  • Track record of identifying and implementing infrastructure optimizations for efficiency, throughput, and reliability.

Preferred Qualifications:

  • Experience with cloud-based EDA infrastructure or hybrid HPC environments.
  • Familiarity with regression management tools, and workflow automation specific to silicon verification.
  • Experience with HPC cluster management, especially using LSF/Platform LSF, in a chip verification or EDA context.

Key Attributes:

  • Analytical, detail-oriented, and proactive in identifying and solving technical problems.
  • Passion for continuous learning and embracing new technologies and methods.
  • Strong organizational abilities and commitment to documentation and process improvement.

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08.05.2025
M

Marvell Sr Staff Optical Product Engineer Taiwan, Hsinchu

Limitless High-tech career opportunities - Expoint
Perform simulations for signal integrity analysis. Perform hands-on high speed signal validation and analysis verification including material, de-embedding, and component characterization. Collaborate cross-functionally with hardware design, system architecture, silicon, and...
Description:

What You Can Expect

In this role you will be responsible for driving the development and implementation of innovative signal integrity and power integrity solutions for Marvell Cloud Optics products

  • Perform simulations for signal integrity analysis
  • Perform hands-on high speed signal validation and analysis verification including material, de-embedding, and component characterization.
  • Collaborate cross-functionally with hardware design, system architecture, silicon, and layout teams to optimize signal and power integrity design based on the simulation data and measurements.
  • Power delivery modeling, simulation, and characterization for die, package, board, and voltage regulators.
  • Provide implementation guidelines and feedback to silicon, package, and hardware design group for electrical signal and power integrity (crosstalk, return loss, jitter, EMI, power supply noise)
  • PCB stackup review and layer assignment for High speed and PDN
  • Document engineering processes and procedures

What We're Looking For

  • Bachelor's degree in Engineering, or any other related field with 6+ years of experience; or a Master's degree or Ph.D. with 3+ years of experience with a proven track record of designs in high volume production.
  • 5+ years of experience with HFSS simulations of PCB, packages and substrates for high speed interfaces (112G SerDes, PCIe Gen5)
  • 5+ years of experience with DC IR drop and PDN analysis for boards with Cadence Sigrity and PowerDC.
  • 5+ years of experience with layout tools like Allegro for design extraction
  • Possesses strong fundamentals in 3D/2D EM simulation tools and transmission line theory
  • Familiarity with electromagnetic compatibility (EMC) and electromagnetic interference (EMI) mitigation techniques
  • Excellent communication skills, both verbal and written, to effectively collaborate with cross-functional teams and present findings to stakeholders

Expected Base Pay Range (USD)

122,700 - 181,600, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.


Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

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23.04.2025
M

Marvell Hardware Validation Intern - Masters Taiwan, Hsinchu

Limitless High-tech career opportunities - Expoint
Working with global teams across Argentina, Singapore, the U.S., and Europe, you will run simulations and verifications using Cadence Virtuoso, collaborating closely with the designer to refine and debug iteratively...
Description:

What You Can Expect

  • Working with global teams across Argentina, Singapore, the U.S., and Europe, you will run simulations and verifications using Cadence Virtuoso, collaborating closely with the designer to refine and debug iteratively until the design meets specifications.

  • Regular meetings with your paired designer ensure collaborative information sharing, integral to Marvell's commitment to partnership and teamwork.

  • As a key contributor, you play a crucial role in the project lifecycle, participating in routine meetings as a technical mentor, layout team, and the broader project team.

  • These interactions include updates on progress and may involve presenting specific issues or solutions encountered during the development of cutting-edge technologies.

  • The dynamic nature of our work ensures continuous learning and knowledge-sharing among colleagues.

What We're Looking For

  • Have fundamental understanding of electrical concepts, likely acquired through a degree in Electrical Engineering (graduate or undergraduate).

  • Know how to use CAD tools to do the implementation layers, microelectronic layers in design that go beyond the schematics.

  • Track record of delivering high-speed or precision analog circuits, preferably in multiple process nodes

  • Have ownership through the full development cycle: floorplan, layout, verification, delivery, and support

  • Assume more responsibility and ownership of tasks, from cells to functional blocks, to higher-level macros, to full interfaces or chips

  • Have excellent communication skills to give status updates to your team, present to global teams in different time zones, and to share information with many different levels of personnel at Marvell

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17.04.2025
M

Marvell Test Engineer Intern - Bachelors Taiwan, Hsinchu

Limitless High-tech career opportunities - Expoint
In this role you will be part of a development team that is responsible for all aspects of engineering design, process development, and productization for Marvell’s optics product line. Contribute...
Description:

What You Can Expect

  • In this role you will be part of a development team that is responsible for all aspects of engineering design, process development, and productization for Marvell’s optics product line.

  • Contribute to optical components development for next generation of product.

  • Implement creative design solutions to accelerate design and tapeout of photonics products.

  • Collaborate closely with CAD and foundry process teams working on the development and support of next generation photonics design flow and design automation.

  • Collaborate with cross-functional teams consisting of Digital and Analog Circuit designers, Signal/Power Integrity, and substrate layout, and system design team.

  • Responsibility changes from time to time depending on the priority of the team and products.​

  • The person is expected to catch up with the new responsibility quickly and execute​.

What We're Looking For

  • Bachelor’s degree in Computer Science, Electrical Engineering, Photonics or related fields and 10+ years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering, Photonics or related fields with 5+ years of experience.

  • A strong understanding of optical active component design, fabrication and validation.

  • Solid background and hands-on experience on high speed modulator or photodiode design and validation.

  • Use of optical and electrical modeling and simulation software to design electro-optical devices and generate GDS level mask data for device fabrication.

  • Solid track record with industry standard tools is expected along with the ability to define and develop PDK.

  • Expertise with design automation EDA software, flows and architecture and a solid understanding of optical simulation tools and related methodologies.

  • Familiarity or direct experience in the standard Si/CMOS/MEMS process technologies required for fabrication and integration of electrical and optical devices.

  • Expected to work with cross-functional team.

  • A proactive self-starter with an exceptional degree of confidence and commitment who does not require constant nudging to move programs forward or effectively complete their execution.

  • Demonstrated history of technical leadership

  • Effective team player.

Show more

These jobs might be a good fit

Limitless High-tech career opportunities - Expoint
Design, implement, and maintain large-scale HPC clusters for EDA workloads, ensuring high availability, fault tolerance, and efficient resource utilization. Manage, configure, and optimize LSF job scheduling systems to support diverse...
Description:
As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to participate in defining the whole organization's design infrastructure, methodology and workflows.


What You Can Expect

  • Design, implement, and maintain large-scale HPC clusters for EDA workloads, ensuring high availability, fault tolerance, and efficient resource utilization.
  • Manage, configure, and optimize LSF job scheduling systems to support diverse verification workflows.
  • Develop, automate, and monitor deployment, configuration, and operational processes for EDAinfrastructure.
  • Collaborate with EDA engineers and designers to refine verification flows to run optimally on the grid.
  • Implement and advance CI/CD pipelines to streamline the deployment, testing, and monitoring of infrastructure and EDA flows.
  • Provide troubleshooting and support for users and the infrastructure.
  • Monitor infrastructure health, performance, and usage; proactively identify, resolve, and document issues.
  • Ensure compliance with security bestpractices, licensemanagement, and data protection requirements.
  • Contribute to architectural innovation and process improvement for future scalability and efficiency.
  • Participate in incident management teams for prompt issue resolution.

What We're Looking For

  • Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related field.

Proficiency with Programming or scripting in languages such as Python, Bash, or Perl for automation and workflow development.

  • Working knowledge of Linux system administration and cluster troubleshooting.

Familiarity withinfrastructure-as-code,configuration management, and monitoring , DevOps; SRE concepts; CI/CD and GitOps.

  • Strong communication and collaboration skills; ability to work in cross-functional teams.
  • Track record of identifying and implementing infrastructure optimizations for efficiency, throughput, and reliability.

Preferred Qualifications:

  • Experience with cloud-based EDA infrastructure or hybrid HPC environments.
  • Familiarity with regression management tools, and workflow automation specific to silicon verification.
  • Experience with HPC cluster management, especially using LSF/Platform LSF, in a chip verification or EDA context.

Key Attributes:

  • Analytical, detail-oriented, and proactive in identifying and solving technical problems.
  • Passion for continuous learning and embracing new technologies and methods.
  • Strong organizational abilities and commitment to documentation and process improvement.

Show more
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