Silicon Packaging Architect jobs at Intel in United States, Phoenix

The ideal candidate should exhibit the following behavioral traits:

• Establish technical credibility, building trust and strong relationships with the customer.
• Ensure our customer successfully evaluates, adopts, and designs products with Intel process technology.
• Highly organized, analytical, and strong team player. Able to clearly synthesize complex information, lead in-depth tactical discussions and deliver results.
• Must be able to provide clear communications with customers and stakeholders.

Qualifications:

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / orschoolwork/classes/research.The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• US Citizenship required.
• Ability to obtain a US Government Security Clearance.
• Bachelors degree in Electrical/Computer Engineering or in a STEM related field of study.
• 8 + years ofexperience/backgroundin Package Design and relevant EDA tools.
• Experience interfacing with customers and/or stakeholders.
• Experience analyzing customer design issues, environments, and define functional specs for EDA vendors.

Preferred Qualifications:

• Active US Government Security Clearance with a minimal of a Secret Level.
• Post Graduate degree in Electrical / Computer Engineering or in a STEM related field of study.
• Experience with EDA implementation or verification tools from either; Cadence, Synopsys or Siemens i.e.:
  • Multi-die/3DIC platform tools such as: Cadence Integrity, Synopsys 3DIC Compiler, Siemens Xpedition Substrate Integrator/Innovator 3D
  • Implementation tools such as : Cadence Virtuoso/Innovus, Allegro (Advanced Package Designer, APD/SiP), Siemens Mentor Xpedition (PCB Layout/XPD), Synopsys Fusion Compiler; and/or
  • Verification tools such as: Siemens Calibre, Synopsys ICV, or Cadence Pegasus

• Experience with design for verification and design for performance: Package Signal Integrity, Power Integrity, manufacturing, and yield.
• Experience analyzing customer design issues, environments, and define functional specs for EDA vendors.
• Experience with scripting in tcl, Python, SKILL, VBScript, etc for design flows, and efficiencies.

Experienced HireShift 1 (United States of America)US, Arizona, Phoenix
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

As an integral part of Intel's new Integrated Device Manufacturer 2.0 (IDM2.0) strategy, we are establishing Foundry Services (FS), a fully vertical, stand-alone foundry business, reporting directly to the CEO. Foundry Services will be a world-class foundry business and major provider of US and European based capacity to serve customers globally.

Foundry Services will be differentiated from other foundries with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe, and a world-class IP portfolio that customers can choose from, including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP's, along with Arm and RISC-V ecosystem IPs. Foundry Services will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages.

This business unit is completely dedicated to the success of its customers with full PandL responsibilities. This model will ensure that our foundry customers' products receive our utmost focus in terms of service, technology enablement, and capacity commitments. FS is already engaged with customers today starting with our existing foundry offerings. We are expanding at a torrid pace to include our most advanced technologies, which are ideal for high-performance applications.

Responsibilities include but are not limited to:

• Drives end to end development for silicon design from concept through tapeout and implements physical layout and routing of the package design.
• Responsible for the definition and development of assembly test chips or bridge die which are used to characterize aspects of chip-package interactions.
• Provides consultation concerning packaging problems and improvements in the packaging process.
• Responds to customer and/or client requests or events as they occur.
• Develops solutions to problems utilizing formal education and judgment.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum Requirements:

• US Citizenship required.
• Ability to obtain and maintain a US Government TS/SCI Security Clearance with Polygraph.
• Bachelor's degree with 1+ years of relevant experience or Master's degree with relevant experience in Mechanical Engineering or Electrical Engineering.Must have the required degree or expect the required degree by December 2025.
• 3+ months experience with microelectronic packageor siliconlayoutdesign usingCadence Virtuoso, Genesys or similar tools.
• 3+ months experience with physical layout aspects of chip design/layout including but not limited to custom layouts, floor plans, schematic generation and schematic to layout conversion and verification.

This position is not eligible for Intel immigration sponsorship.

Preferred Qualifications:

• Active US Government Security Clearance with a minimal of a Secret Level
• Experience with device design, and analog/mixed signal layout
• Experience with ICCompiler and ICWorkbench
• Readiness to troubleshoot a wide variety of physical design/layout issues.

College GradShift 1 (United States of America)US, Arizona, Phoenix
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

$104,890.00-$148,080.00

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Responsibilities

• Define Package Architecture across Intel's product portfolios (CPUs, Chipsets, SOC designs and more) as part of the Assembly and Test Technology Development group.
• Work with the Si and Board design teams to define and implement a co-design strategy which would optimize product performance and cost at the package and system level.
• Understand packaging technology development FMEAs and product packaging requirements - both physical and electrical.
• Work closely with Intel and external customers on advanced design nodes to establish design flows for advanced package architectures.
• Direct technical aspects of the Package Architecture process including conducting early route studies, creation of specifications, providing guidance for electrical analysis and supervision of production layouts.
• Collaborate with EDA partners on advancing package design tools and identify most efficient design methods and serve as the technical expert on advanced package architectures and design tools as well as consult on design and implementation issues.
• Work with a cross functional team including silicon IP design, package and PCB platform to define and co-optimize package solutions. This position determines creative design approaches and solutions based on formal education and judgement, works with the design and layout teams to implement those solutions.

Required Background and Experience:

• Good technical understanding in the areas of Si +Package - Board interaction.
• Solid background in semiconductor fabrication and packaging
• Self-motivated engineer who has strong technical background in both design and electrical analysis.
• Experience with design and simulation tools.
• Strong analytical ability and problem-solving skills: identifying, isolating, and debugging issues and providing creative solutions. - Ability to work independently and at various levels of abstraction
• Strong organization, time management, and communication skills, self-motivated.
• Exhibit the following behavioral traits:
  • Strong analytical ability and problem-solving skills like identifying, isolating, and debugging issues and providing creative solutions.
  • Ability to work independently and at various levels of abstraction.

Qualifications:

Required Qualifications:

• US Citizenship required.
• Ability to obtain a US Government Security Clearance
• Ph.D. or master’s in electrical engineering, chemical engineering, mechanical engineering, material science or similar field.
• 10+ years and in-depth knowledge/background in Package, PCB design, or IC digital design.

Preferred Qualifications:

• Active US Government Security Clearance with a minimal of a Secret Level.
• Experience and knowledge with assembly process, test and characterization techniques.

Experienced HireShift 1 (United States of America)US, Arizona, Phoenix
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Key Responsibilities:

• Design and Development: Develop, test, and maintain factory automation systems, including manufacturing execution systems (MES), Middleware, defect metrology, station controller, and factory data systems.

• Optimization and Integration: Analyze, prototype, and enhance automation solutions that improve factory performance, output, and cycle time while meeting environmental constraints.

• Collaboration and Innovation: Partner with cross-functional teams (automation engineers, manufacturing planners, industrial engineers) to create and implement data-driven solutions using advanced technologies such as machine learning, statistical analysis, and optimization algorithms.

• Documentation and Support: Provide input into technical documentation, create product manuals, and support post-deployment systems to ensure optimal performance and scalability. Adapt and prioritize work based on the changing business needs.

The candidate should also exhibit the following behavioral traits and/or skills:

• Problem-solving: Strong analytical skills to address complex manufacturing challenges and develop innovative solutions.

• Collaboration: Excellent teamwork and communication abilities to collaborate with engineers and stakeholders.

• Adaptability: Comfortable working in ambiguous environments and self-motivated to drive solutions.

• Attention to Detail: Strong organizational skills to manage multiple projects and ensure accurate execution.

• Willingness to quickly learn and master various facets of Intel's business to deliver value-driven solutions.

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:

• Bachelor's degree in computer science, Computer Engineering, or a related field OR Master's or PhD degree in Computer Science, Computer Engineering, or a related field and 6+ years relevant experience.

• US Citizenship required.

• Ability to obtain and maintain a US Government Security Clearance.

• 6+ years of experience in software development, design, and testing, with a focus on factory automation or similar mission-critical systems (such as web service development, cloud application development).

• 6+ years' experience in C# and .NET.

• 6+ years' experience in leading factory automation software development teams from concepts to shipping finished products.

Preferred Qualifications:

• Master's or PhD degree in computer science, computer engineering, or a related field and 5+ years' experience.

• Active US Government Security Clearance.

• Experience semiconductor manufacturing processes, factory automation, manufacturing execution planning, production control, and dispatching systems.

• Experience with Agile methodologies and automated testing and deployment processes.

• Experience with Python (Pandas, NumPy, SciPy) and graphical user interface (GUI) development, particularly using Applied Materials' Advanced Productivity Family (APF and FAB300).

• Experience with machine learning, data mining, and advanced optimization tools like CPLEX Optimization Studio.

• Python programming skills

• Experience with troubleshooting and debugging skills in production environments.

• Experience with at least two of the following: RDBMS Systems (Oracle, MS-SQL, Postgres etc.)

• Software/Systems Development Life Cycle (SDLC)

• DevOps Practices

• System architecture definition and documentation

• Experience with systems engineering (e.g., Windows, SAN, Firewalls, WAN, BCP, Databases).

Experienced HireShift 1 (United States of America)US, Arizona, Phoenix
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

The ideal candidate should exhibit the following behavioral traits:

• Self-driven and results-oriented and able to multi-task and work in a fast-paced worldwide environment.
• Analytical problem-solving skills.
• Effective communication skills and experience in collaborating with stakeholders and customers.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. The minimum requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and / orschoolwork/classes/research.Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications

• US Citizenship required.
• Ability to obtain a US Government Security Clearance.
• Bachelor's degree in Electrical / Computer Engineering, Electronics Engineering, Computer Science, or in a STEM related field of study.
• 8+ years of design experience in Package, or IC digital design OR 8+ years of EDA Tool experience.
• Must have the EDA implementation or verification tools from either; Cadence, Synopsys or Siemens i.e.:
• Multi-die/3DIC platform tools such as:
  Cadence Integrity, Synopsys 3DIC Compiler, Siemens Xpedition Substrate Integrator/Innovator 3D.
• Implementation tools such as
  : Cadence Virtuoso/Innovus, Allegro (Advanced Package Designer, APD/SiP), Siemens Mentor Xpedition (PCB Layout/XPD), Synopsys Fusion Compiler.
• Verification tools such as:
  Siemens Calibre, Synopsys ICV, or Cadence Pegasus.
• Experience in design for verification and design for performance: (Signal Integrity, Power Integrity, manufacturing, and/or yield.)
• Experience interfacing with customers and/or stakeholders from remote sites worldwide and analyzing customer design issues, environments, and define functional specs for EDA vendors.
• Experience with scripting in tcl, Python, SKILL, VBScript, or Perl to automate design flows.

Preferred Qualifications:

• Post Graduate degree in Electrical / Computer Engineering, Electronics Engineering, Computer Science, or in a STEM related field of study.
• Active US Government Security Clearance with a minimum of a Secret level.
• Experience with Silicon or assembly process, test and characterization techniques.

Experienced HireShift 1 (United States of America)US, Arizona, Phoenix
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Description:

Silicon Packaging Design Engineer job responsibilities include but not limited to:

• Drives end-to-end development for substrate design from concept through tapeout and implements physical layout and routing of the package design.
• Follows substrate design rules, conducts routing studies to establish design, performance, and cost tradeoffs.
• Works closely with silicon and hardware teams to optimizesilicon/package/boardperformance and pinout.
• Defines substrate design rules, conducts internal and external reviews, and resolves DRCs to optimize package design.
• Completes documentation and collateral into the system of record tool.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum Qualifications:

• US Citizenship required.
• Ability to obtain a US Government Security Clearance.
• Bachelor's degree in Electrical / Mechanical Engineering, or in a STEM related field of study.
• 3+ months experience with microelectronic package or PCB physical layout design using package design tools such as Siemens Xpedition, Cadence Allegro, or CAD.

Preferred Qualifications:

• Active US Government Security Clearance with a minimal of a Secret Level.
• Master's degree in in Electrical / Mechanical Engineering, or in a STEM related field of study.
• Performing package I/O routing starting day one.
• Strong analytical ability and problem-solving skills: identifying, isolating, and debugging issues and providing creative solutions.
• Microelectronic package substrate technology development.
• Package design tools such as Package Layout Automation (PLA) and FIELD.
• Microelectronic package electrical modeling and simulation tools such as PowerDC, HyperLynx, Q3D, and HFSS.
• Extract signal integrity and/or power delivery electrical models and run AC/DC/Frequency Domain simulations.
• Scripting using Python, VB, C, and or other languages.

College GradShift 1 (United States of America)US, Arizona, Phoenix
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.