Emulation Prototyping Architect Soc Performance/power jobs at Arm in India, Bengaluru

Responsibilities

• As a creative design engineer with a knowledge of subsystems and SoCs you will be part team developing Subsystems & SoCs.
• You will work with Architects to capture the requirements and develop Micro-architecture specifications for one or more SOC areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc.
• Key responsibilities will include writing micro-architecture and work with Design team to deliver high quality RTL.
• Collaborate with verification and Validation team to review test plans, and help debug design issues. Closely work with the Power and Performance analysis team to evaluate and improve Subsystem/SOC PPA.
• Contribute to developing and improving the design methodologies.
• Guide and support other members of the team for overall Program success. Balance other opportunities such as working with Project Management on activities, plans, and schedules

Required Skills and Experience:

• Bachelors or Master’s degree or equivalent experience in Electronics/Electrical Engineering.
• Experience of 8+ years working in design of complex compute subsystems or SoCs
• Expertise in developing Micro-architecture and Design specifications for the SoC Infrastructure areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc.
• Solid understanding of digital hardware design and Verilog HDL. Experience in development and Tapeout of Complex SoC and RTL Development.
• Experience leading and developing RTL for Subsystems or SoCs.
• Conversant with Lint, CDC and RDC flows.
• Good communication (written, verbal, presentations) skills.
• Experience with Perl, Python or other scripting language

Desired Skills and Experience:

• Experience with ARM-based designs and/or ARM System Architectures
• Experience developing subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet
• Experience with SystemVerilog and verification methodologies – UVM/OVM
• Experience leading small teams or projects
• Experience or knowledge in the following areas
• Synthesis and timing analysis
• Static design checks, including CDC, RDC, X-Propagation, Linting
• Power management techniques
• DFT and physical implementation

As part of the methodology team, you will be responsible for developing and leading sophisticated power estimation and optimization methodologies at the netlist (gate-level) stage across SoC and IP designs. You will drive correlation strategies, automation flows, and accuracy improvements to ensure power estimates are tightly aligned with final silicon behavior. This role requires deep technical expertise in power analysis tools, a strong understanding of low-power design techniques, and collaboration with multi-functional teams across the design and verification cycle.

• Define and drive netlist-level power estimation methodologies using industry-leading tools (e.g., Synopsys PrimeTime PX, Cadence Voltus).
• Establish and maintain correlation frameworks between RTL and gate-level power, and between estimated and silicon power.
• Develop automated flows for toggling activity generation, vector-based and vectorless power estimation, and regression reporting.
• Analyze power consumption trends and identify hotspots; provide recommendations for low-power design optimization.
• Collaborate with RTL design, physical design, DFT, and architecture teams to ensure early and accurate power signoff.
• Lead methodology development for corner analysis, dynamic/static power separation, and voltage scaling assessments.
• Support signoff reviews, audits, and compliance to power specifications and constraints.
• Provide mentorship and technical leadership within the team and across global sites.

• Proven experience of 5+ years in power estimation, optimization, and methodology development at the gate-level/netlist stage.
• Hands-on expertise with tools such as Synopsys PrimeTime PX, Cadence Voltus, and related signoff flows.
• Strong understanding of digital design principles, low-power architecture techniques, clock gating, and multi-voltage domains.
• Proficient in scripting (Python, Perl, TCL) to develop scalable and automated power analysis flows.
• Demonstrated experience in analyzing switching activity data (SAIF/VCD/FSDB) and correlating to real application workloads.
• Confirmed ability to handle large SoC designs and deliver accurate power metrics under tight schedules.
• Excellent problem-solving skills, attention to detail, and ability to drive technical discussions and decisions.

• Experience with UPF/CPF power intent validation and integration.
• Exposure to thermal and IR-drop analysis in relation to power consumption.
• Familiarity with AI/ML-based power modeling or anomaly detection.
• Previous contributions to methodology deployment in domains such as mobile, automotive, or server-grade SoCs.
• Participation in EDA tool evaluations, benchmarking, and vendor teamwork.
• Publications or presentations in technical forums (e.g., SNUG, DVCon, DAC) related to power estimation or optimization.

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence
• Deliver on your promises

As a Security Engineer – Fuzzing Specialist, you will own and evolve our coverage-guided fuzzing program. Your mission is to uncover hard-to-reach security flaws before attackers do, drive fixes to closure, and help product teams to embrace dynamic testing like fuzzing. You’ll scout for new attack surfaces, craft high-performance fuzzing harnesses, and design custom sanitisers that push the state of the art. Success means measurable coverage gains, actionable crash reports, and products that ship with provable resilience.

• Map & prioritise fuzzing surfaces across services, libraries, APIs, and protocols; maintain a living risk-based roadmap.
• Design, build, and extend fuzzing harnesses (libFuzzer, AFL++, Honggfuzz, etc.) that improve code-path exploration and minimise false positives.
• Continuously improve coverage by growing seed corpus, deploying targeted mutation strategies, and integrating new instrumentation techniques.
• Automate crash triage & root-cause analysis; distinguish exploitable vulnerabilities from benign faults and drive CVE-level findings to remediation.
• Develop custom sanitisers to expose classes of bugs traditional fuzzing misses.
• Validate fixes & guard against regressions through differential fuzzing and regression corpora.
• Assess external disclosures (bug bounties, supply-chain advisories) to determine fuzzing detectability and refine harnesses when gaps are found.
• Document, report, and share insights — from coverage metrics to post-mortems to create data-driven security.

• 1+ years in application or product security with a deep focus on coverage-guided fuzzing.
• Hands-on expertise with at least one modern fuzzing framework (e.g., libFuzzer, AFL++, Honggfuzz).
• Proficient in C/C++ plus strong scripting ability in Python for automation.
• Solid understanding of memory-safety vulnerabilities, undefined behaviour, sanitisers, and compiler instrumentation.
• Demonstrated ability to triage crashes using debuggers, profilers, and reverse-engineering tools (gdb/lldb, IDA/Ghidra).
• Excellent written communication for documenting findings and influencing engineering teams.

• Contributions to open-source fuzzing tools, sanitisers, or security research publications.
• Knowledge of distributed fuzzing at scale (GCP/AWS, Kubernetes, or bare-metal clusters).
• Familiarity with kernel, embedded, or firmware fuzzing (e.g., Syzkaller, QEMU-based harnesses).
• Background in reverse engineering, static analysis or symbolic execution.
• Experience integrating fuzzing into CI/CD pipelines and tracking coverage metrics.

As part of the methodology team, you will be responsible for developing and leading sophisticated power estimation and optimization methodologies at the netlist (gate-level) stage across SoC and IP designs. You will drive correlation strategies, automation flows, and accuracy improvements to ensure power estimates are tightly aligned with final silicon behavior. This role requires deep technical expertise in power analysis tools, a strong understanding of low-power design techniques, and collaboration with multi-functional teams across the design and verification cycle.

• Define and drive netlist-level power estimation methodologies using industry-leading tools (e.g., Synopsys PrimeTime PX, Cadence Voltus).
• Establish and maintain correlation frameworks between RTL and gate-level power, and between estimated and silicon power.
• Develop automated flows for toggling activity generation, vector-based and vectorless power estimation, and regression reporting.
• Analyze power consumption trends and identify hotspots; provide recommendations for low-power design optimization.
• Collaborate with RTL design, physical design, DFT, and architecture teams to ensure early and accurate power signoff.
• Lead methodology development for corner analysis, dynamic/static power separation, and voltage scaling assessments.
• Support signoff reviews, audits, and compliance to power specifications and constraints.
• Provide mentorship and technical leadership within the team and across global sites.

• 10+ years of proven experience in power estimation, optimization, and methodology development at the gate-level/netlist stage.
• Hands-on expertise with tools such as Synopsys PrimeTime PX, Cadence Voltus, and related signoff flows.
• Strong understanding of digital design principles, low-power architecture techniques, clock gating, and multi-voltage domains.
• Proficient in scripting (Python, Perl, TCL) to develop scalable and automated power analysis flows.
• Demonstrated experience in analyzing switching activity data (SAIF/VCD/FSDB) and correlating to real application workloads.
• Confirmed ability to handle large SoC designs and deliver accurate power metrics under tight schedules.
• Excellent problem-solving skills, attention to detail, and ability to drive technical discussions and decisions.

• Experience with UPF/CPF power intent validation and integration.
• Exposure to thermal and IR-drop analysis in relation to power consumption.
• Familiarity with AI/ML-based power modeling or anomaly detection.
• Previous contributions to methodology deployment in domains such as mobile, automotive, or server-grade SoCs.
• Participation in EDA tool evaluations, benchmarking, and vendor teamwork.
• Publications or presentations in technical forums (e.g., SNUG, DVCon, DAC) related to power estimation or optimization.

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence
• Deliver on your promises

Job Overview:

It would also be desirable if you have experience with media, graphics or imaging flows and driver/middleware stack development.

Responsibilities:

• Design and implement software components that meet functional safety requirements (e.g., ISO 26262, IEC 61508).
• Work to bring function safety to existing code.
• Develop and maintain documentation to support safety certification and compliance audits.
• Collaborate with safety engineers, hardware teams, and software architects to define software safety requirements and architectures.
• Support software integration, verification, and validation processes in safety-critical systems.
• Contribute to process improvements and tooling for safety-focused software development workflows

Required Skills and Experience:

• Strong proficiency in C development, particularly in embedded or system-level programming.
• Well-versed in functional safety principles, including hazard analysis, safety goals, and ASIL decomposition.
• Motivation and ability to work on frontend tasks using JavaScript.
• Hands-on experience with safety standards such as ISO 26262 or IEC 61508.

“Nice To Have” Skills and Experience :

• Experience with safety analysis tools and methods (e.g., FMEA, FMEDA, fault injection).
• Knowledge of MISRA C/C++ or other safety-related coding standards.
• Background in developing software for automotive, aerospace, or industrial control systems.
• Familiarity with safety certification processes and documentation requirements.
• Knowledge of media, imaging or rendering pipelines.

In Return:

As part of the methodology team, you will play a crucial role in developing, enhancing, and deploying RTL-level power estimation and analysis methodologies across a range of SoC and IP design projects. This position requires close collaboration with design, verification, and physical implementation teams to ensure early power estimation accuracy, scalable methodology integration, and automation for power-aware design. The ideal candidate brings hands-on experience in RTL power estimation, scripting for tool automation, and a deep understanding of power intent specifications and constraints.

• Develop and maintain RTL power estimation methodologies using industry-standard tools (e.g., Synopsys, Cadence, Ansys).
• Work with design teams to define power analysis strategy, monitor early power trends, and deliver actionable feedback.
• Automate power estimation and reporting flows integrated into regression infrastructure.
• Validate and correlate RTL power estimates with gate-level and post-layout results.
• Support power-aware verification and ensure alignment with UPF/CPF-based power intent.
• Collaborate with multi-functional teams (design, verification, PD, DFT) to drive power closure.
• Develop documentation, training materials, and standard methodologies to enable global adoption.

• 3-6 years of proven experience in RTL power estimation, analysis, or methodology development.
• Hands-on experience with power estimation tools such as Synopsys PrimePower, Cadence Joules, Ansys PowerArtist, etc.
• Strong understanding of RTL design, power intent formats (UPF/CPF), and switching activity generation (VCD/SAIF).
• Proficiency in scripting languages such as Python, Perl, or TCL for automation.
• Solid debugging and analytical skills to interpret and optimize power numbers.
• Familiarity with digital design flow, simulation, and verification concepts.
• Effective communication and teamwork skills.

• Experience with power-aware verification and formal techniques.
• Knowledge of gate-level power estimation and correlation techniques.
• Exposure to AI/ML-based power optimization or prediction models.
• Familiarity with SoC-level integration challenges and power modeling for IPs.
• Contributions to flow development in large-scale or multi-site environments.
• Prior experience working in automotive, mobile, or high-performance compute SoCs.

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence
• Deliver on your promises

As part of the methodology team, you will lead the development, improvement, and deployment of low power structural check methodologies across multiple SoC and IP projects. This role involves designing automated flows for UPF/CPF consistency, power domain integrity, and structural rule validation at both RTL and netlist levels. You will collaborate closely with design, verification, and EDA partners to ensure robust, scalable, and high-coverage power-aware design signoff strategies across technology nodes and product segments.

• Develop and maintain low-power structural check methodologies (UPF/CPF validation, isolation, level shifters, retention, domain crossings).
• Build automated flows using tools like Synopsys VC LP, SpyGlass-LP, and Conformal LP.
• Ensure power intent consistency and early issue detection through collaboration with design and verification teams.
• Integrate structural checks into signoff regressions with high coverage and low false positives.
• Work with vendors and internal teams to enhance tools, debug issues, and improve efficiency.
• Drive global adoption through documentation, training, and support.
• Assist in audits, quality reviews, and milestone checks.

• 5+ years of Strong background in low-power structural methodologies and UPF/CPF-based flows.
• Deep understanding of power intent specs, domain partitioning, isolation, and retention.
• Hands-on experience with tools like VC LP, SpyGlass-LP, or Cadence CLP.
• Skilled in scripting (Python, Perl, TCL) for flow automation.
• Experience with large SoC/IP designs across advanced nodes.
• Confirmed ability to debug structural issues and drive closure.
• Strong communication and documentation skills.

• Experience with formal verification or functional simulation for power-aware designs.
• Knowledge of complex power analysis and correlation with structural checks.
• Exposure to hierarchical low-power signoff strategies in multi-voltage or multi-power domain SoCs.
• Familiarity with power-aware DFT, scan strategies, and low-power aware synthesis flows.
• Participation in industry working groups (e.g., Accellera UPF), technical conferences, or publications.
• Involvement in tool benchmarking, vendor collaborations, and internal tool qualification projects.

We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding!

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence
• Deliver on your promises