ARM RTL Power Estimation Methodology Engineer 

India, Karnataka, Bengaluru 

533977710

As part of the methodology team, you will play a crucial role in developing, enhancing, and deploying RTL-level power estimation and analysis methodologies across a range of SoC and IP design projects. This position requires close collaboration with design, verification, and physical implementation teams to ensure early power estimation accuracy, scalable methodology integration, and automation for power-aware design. The ideal candidate brings hands-on experience in RTL power estimation, scripting for tool automation, and a deep understanding of power intent specifications and constraints.

• Develop and maintain RTL power estimation methodologies using industry-standard tools (e.g., Synopsys, Cadence, Ansys).
• Work with design teams to define power analysis strategy, monitor early power trends, and deliver actionable feedback.
• Automate power estimation and reporting flows integrated into regression infrastructure.
• Validate and correlate RTL power estimates with gate-level and post-layout results.
• Support power-aware verification and ensure alignment with UPF/CPF-based power intent.
• Collaborate with multi-functional teams (design, verification, PD, DFT) to drive power closure.
• Develop documentation, training materials, and standard methodologies to enable global adoption.

• 3-6 years of proven experience in RTL power estimation, analysis, or methodology development.
• Hands-on experience with power estimation tools such as Synopsys PrimePower, Cadence Joules, Ansys PowerArtist, etc.
• Strong understanding of RTL design, power intent formats (UPF/CPF), and switching activity generation (VCD/SAIF).
• Proficiency in scripting languages such as Python, Perl, or TCL for automation.
• Solid debugging and analytical skills to interpret and optimize power numbers.
• Familiarity with digital design flow, simulation, and verification concepts.
• Effective communication and teamwork skills.

• Experience with power-aware verification and formal techniques.
• Knowledge of gate-level power estimation and correlation techniques.
• Exposure to AI/ML-based power optimization or prediction models.
• Familiarity with SoC-level integration challenges and power modeling for IPs.
• Contributions to flow development in large-scale or multi-site environments.
• Prior experience working in automotive, mobile, or high-performance compute SoCs.

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