ARM Power Estimation Methodology Engineer 

India, Karnataka, Bengaluru 

861947636

As part of the methodology team, you will be responsible for developing and leading sophisticated power estimation and optimization methodologies at the netlist (gate-level) stage across SoC and IP designs. You will drive correlation strategies, automation flows, and accuracy improvements to ensure power estimates are tightly aligned with final silicon behavior. This role requires deep technical expertise in power analysis tools, a strong understanding of low-power design techniques, and collaboration with multi-functional teams across the design and verification cycle.

• Define and drive netlist-level power estimation methodologies using industry-leading tools (e.g., Synopsys PrimeTime PX, Cadence Voltus).
• Establish and maintain correlation frameworks between RTL and gate-level power, and between estimated and silicon power.
• Develop automated flows for toggling activity generation, vector-based and vectorless power estimation, and regression reporting.
• Analyze power consumption trends and identify hotspots; provide recommendations for low-power design optimization.
• Collaborate with RTL design, physical design, DFT, and architecture teams to ensure early and accurate power signoff.
• Lead methodology development for corner analysis, dynamic/static power separation, and voltage scaling assessments.
• Support signoff reviews, audits, and compliance to power specifications and constraints.
• Provide mentorship and technical leadership within the team and across global sites.

• Proven experience of 5+ years in power estimation, optimization, and methodology development at the gate-level/netlist stage.
• Hands-on expertise with tools such as Synopsys PrimeTime PX, Cadence Voltus, and related signoff flows.
• Strong understanding of digital design principles, low-power architecture techniques, clock gating, and multi-voltage domains.
• Proficient in scripting (Python, Perl, TCL) to develop scalable and automated power analysis flows.
• Demonstrated experience in analyzing switching activity data (SAIF/VCD/FSDB) and correlating to real application workloads.
• Confirmed ability to handle large SoC designs and deliver accurate power metrics under tight schedules.
• Excellent problem-solving skills, attention to detail, and ability to drive technical discussions and decisions.

• Experience with UPF/CPF power intent validation and integration.
• Exposure to thermal and IR-drop analysis in relation to power consumption.
• Familiarity with AI/ML-based power modeling or anomaly detection.
• Previous contributions to methodology deployment in domains such as mobile, automotive, or server-grade SoCs.
• Participation in EDA tool evaluations, benchmarking, and vendor teamwork.
• Publications or presentations in technical forums (e.g., SNUG, DVCon, DAC) related to power estimation or optimization.

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