As a creative design engineer with a knowledge of subsystems and SoCs you will be part team developing Subsystems & SoCs.
You will work with Architects to capture the requirements and develop Micro-architecture specifications for one or more SOC areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc.
Key responsibilities will include writing micro-architecture and work with Design team to deliver high quality RTL.
Collaborate with verification and Validation team to review test plans, and help debug design issues. Closely work with the Power and Performance analysis team to evaluate and improve Subsystem/SOC PPA.
Contribute to developing and improving the design methodologies.
Guide and support other members of the team for overall Program success. Balance other opportunities such as working with Project Management on activities, plans, and schedules
Required Skills and Experience:
Bachelors or Master’s degree or equivalent experience in Electronics/Electrical Engineering.
Experience of 8+ years working in design of complex compute subsystems or SoCs
Expertise in developing Micro-architecture and Design specifications for the SoC Infrastructure areas such as Power Management, Boot, Debug, Clocks, Resets, DDR, RAS, Security, Access Control, Die to Die etc.
Solid understanding of digital hardware design and Verilog HDL. Experience in development and Tapeout of Complex SoC and RTL Development.
Experience leading and developing RTL for Subsystems or SoCs.
Conversant with Lint, CDC and RDC flows.
Good communication (written, verbal, presentations) skills.
Experience with Perl, Python or other scripting language
Desired Skills and Experience:
Experience with ARM-based designs and/or ARM System Architectures
Experience developing subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet
Experience with SystemVerilog and verification methodologies – UVM/OVM
Experience leading small teams or projects
Experience or knowledge in the following areas
Synthesis and timing analysis
Static design checks, including CDC, RDC, X-Propagation, Linting