In this position,
� You will participate in the development and validation of various Hard-IPs for various process technologies. You will focus on executing to pre-Silicon validation plans as per the hard-IP/product release schedule and deliverables, and also carry out debug, report failures, report potential failures and help with root-causing the failures. You may also interface with other validation teams and will also work on improving existing processes and validation methodologies.
� You will be required to create verification test plans, drive/participate in discussions across various disciplines to get a clear understanding of requirements, develops the architecture and design of the verification environment in OVM/UVM for pre-silicon RTL verification, develops/run/debug tests in SystemVerilog, mentors other engineers in using the verification infrastructure and creating test benches. � You should be able to support debugs on sub-system/SOC that use the IP provided. You should also be able to support post-silicon/platform failures related to the IP provided.
� You may be required to contribute to the development and maintenance of long term design verification strategy. You should track progress of self/sub-team to achieve goals timely, provide indicators and guidance to management on issues and roadblocks on a timely basis and be able to work with teams across different geographies.

� You should possess a Masters or Bachelor's degree in Electrical/Electronics/Computer Engineering, with 3-8 years of relevant experience in the industry.
Additional qualifications/skills include:
� Experience in developing high quality validation plans, collecting and analyzing the test results and being able to debug the failures to RTL/gate/schematic level
� Strong problem-solving and teamwork skills, and strong verbal and written communication skills
� Ability to produce results in a challenging, fast-paced, multi-site, multi-group environment
� Good working knowledge of HDLs and HVLs like VHDL, Verilog HDL, SystemVerilog is a must.
� Good working knowledge of either one or more of reuse methodologies like VMM/OVM/eRM/AVM/RVM, preferably UVM.
� Good understanding of IO design and validation methodologies, and electrical and system validation issues related to analog, digital, and mixed-signal circuits/IPs would be a big plus.
� Understanding of design-for-testability and design-for-reliability methodologies would be a big plus.
� Work experience with at least one other verification aspect like Performance modeling, Formal verification, Gate Level verification, Emulation, etc. would be an added advantage.
� Proficiency in scripting languages and utilities including Make, Perl, Python, etc. will be a bonus.
� Experience in mixed signal IP design verification is a plus with protocols such as PCI-Express, SATA, USB, Display I/O, MIPI, Ethernet, etc. and AMBA, JTAG, PIPE, etc. is desired
� Should be able to contribute as IC or technically leading a group of team as per requirement