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As a Senior Hardware Engineer on the Accelnet hardware team, you will be responsible for building, testing, and deploying networking acceleration on Azure -- the largest deployment of FPGA SmartNICs in the world. You will develop the infrastructure for next-generation Software-Defined Networking (SDN), including arbitrary packet manipulations, reducing virtualization overhead, and improving connection setup performance for general and custom networking protocols. You should be able to drive projects with both hardware and software teams, and both inside and outside of Microsoft.
This is a unique opportunity for hardware developers to see their Register Transfer Level (RTL) code go to production within weeks instead of years, or for software developers to tap into the performance and efficiency of customized hardware. Come help build one of the few truly hyperscale global clouds, with innovations possible at every level of the computing stack.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until October 16, 2025.
• Design, propose and oversee the analysis/evaluation of hardware architectures
• Design and code RTL modules written in Verilog / SystemVerilog and targeting FPGAs
• Simulate and perform hardware-based testing, debug, and verification of FPGA designs
• Scripting and basic software development in support of hardware design
• Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment
• Handle a DevOps role with occasional on-call responsibilities for resolving customer issues in production
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