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What you will be doing:
Work on the cutting edge standard cell libraries and/or custom ROM (Read Only Memory) modules in deep submicron technologies.
Drive the concepts of the transistor level standard cell circuit design, modeling and performance analysis process.
Lead the function/feasibility verification of new ROM designs and the setup of new design flows.
Provide creative new insights to support existing tools and flows and develop new simulations to perform design margin evaluations.
Collaborate with cross function teams with regards to standard cell design improvement opportunities. We will improve on our quality checks on the libraries.
What we need to see:
MS in Electrical or Computer Engineering (or equivalent experience).
We are looking for strong background in deep submicron process issues.
Deep understanding of the design and verification of standard cell libraries and/or custom ROMs.
Hands-on experience running SPICE simulation, and capability to adapt to new simulation tools.
Experience with running EM/IR, aging, noise, margin, and high sigma variation simulations.
Hands-on experience of DRC/LVS debug.
Experience of designing flip flops, level shifters, math cells and/or custom ROMs, register files, SRAM.
Strong proficiency in scripting language, such as, Perl, Tcl, Make, and automation methods/algorithms a certain plus.
Excellent teamwork, communication and analytical skills.
You will also be eligible for equity and .
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