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What you'll be doing:
You will lead all aspects of physical design and implementation of CPU cores and other ASIC IP targeted at the networking markets.
Be exposed and work on variety of complicated designs (including high density and high speed blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis and physical verification.
What we need to see:
You are pursuing a BSEE / MSEE (or equivalent experience).
Able to chip in to design flow development and debugging.
Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys(ICC2/DC/PT/STAR/ICV),Cadence(Genus/Innovus/Tempus)and other major EDA companies.
To be successful you should possess strong analytical and debugging skills.
Proficiency using Python, Perl, Tcl, Make scripting is helpful.
You will also be eligible for equity and .
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