Microsoft Senior Design Verification Engineer 

Taiwan, Taoyuan City 

969315965

engineers to help achieve that mission.

Artificial Intelligence System on Chip (is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery,and industry knowledge to envision and implement future technical solutions that will manage andthe Cloud infrastructure.

Required/Minimum Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
• 5+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), SystemVerilogand Verification Fundamentals
• 3+ years of debugging RTL (Verilog) designs as well as simulation and/or emulation environments
• 3+ years experience with verification for product from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C/C++ and Universal Verification Methodology (UVM)
• 3+ years experience with scripting language such as Python or Perl or shell scripts.

Other requirements:

• Abilityto meet Microsoft, customer and/or government security screening requirementsarerequired for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate willbe requiredto provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable

Additional or Preferred Qualifications

• 10+ years of design verification experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental
• In depth knowledge of verification principles, testbenches, stimulus generation, and UVM based test environments
• Verification experience for an IP or SS or SOC related to CPUs, VPUs, GPUs, Tensor unit, or similar
• Knowledge of System Verilog class, constraints, coverage and assertions.
• Experience in scripting languages such as Python or Perl
• Hands-on experience in Formal property verification, formal verification of computational data path designs

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until October 20th, 2025.

• Perform pre-silicon verification for complex IP, including creatingtestplans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues,runningandmaintainingregression suites, and closing coverage.
• Interact with architects and design engineers to createtestplanscovering verification strategy, test requirements, and test environments for IP/SS/SOC level verification.
• Define verification strategy, requirements, test environments for IP/SS/SOC level verification.
• Create test-plans and write tests to provide complete features coverage.
• Develop and implement technical solutions to complex quality and design challenges.
• Develop verification components like scoreboards, sequences, constraints,assertionsand functional coverage.
• Triage and debug testbench, simulation, and emulation fails.
• DevelopMakefilesand scripts for verification infrastructure.
• Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.
• Collaborate with teams across sites and geographies.