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Tesla IC Package Layout Engineer 
United States, California, Palo Alto 
953160065

13.08.2024

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What You’ll Do
  • Design: Set up layer stackup, design constraints (Physical, Space and Electrical), execute layout, optimize design based on design review and SI/PI simulation result
  • Feasibility Study: Review die floor plan, bump map, perform fan-out study and mockup design
  • Review/validation: Conduct DRC/DFM check based on design rules. Perform LVS check based on Verilog netlist and schematic
What You’ll Bring
  • Engineering Degree in a relevant field, or equivalent experience
  • 2+ years hands on experience with flip chip IC package design
  • Proficient in Cadence APD+ and SiP Layout
  • Familiar with Unix, Python, TCL, MATLAB
  • Basic transmission line theory, signal and power integrity fundamentals

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