Qualcomm Memory System Architect – Cloud SoC Architecture 

United States, California 

949365818

Job Area:

Engineering Group, Engineering Group > SoC Architecture

Qualcomm’s growing Cloud & Data Center Business Unit SoC Architecture team analyzes requirements and SoC & system architecture to define the next-generation cloud AI and other data center products. Memory architecture has become a pivotal technology track for these products. Cloud AI workloads especially demand exceptional memory bandwidths and large capacities. Meanwhile, the memory technology industry is transforming, leading to a variety of opportunities and choices.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or related field and 8+ years of Systems Engineering or related work experience.

Master's degree in Electrical Engineering, Computer Science, or related field and 7+ years of Systems Engineering or related work experience.

PhD in Electrical Engineering, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.

• 2+ years of experience in one or more system architecture technology areas and products (e.g., Power System, Shared Resource Management, Limits/Thermal Management, Hardware Islands).

You will engage with customers and product managers to understand product requirements; research and analyze potential memory technologies; engage directly with memory vendors and suppliers to evaluate options and drive requirements; quantify the tradeoffs; recommend technical direction with robust justification; and drive the Cloud BU and Qualcomm technology and engineering organizations to successfully execute on that technical direction. Throughout the process, you will effectively communicate and collaboratively engage with the other SoC & IP architects, designers, systems engineers, product managers, and software teams to define Memory System solutions enabling market-leading Cloud AI and Data Center products.

Skills/Experience:

• Outstanding memory architecture expertise on SRAM, DRAM, DDR, LPDDR, HBM, GDDR and emerging memory technologies such as STT-MRAM, PIM, etc.

• Understanding internal memory technology organization, including DRAM bank & array arrangement, rows and columns, row buffer operation, internal data bus pathways, refresh, power state control, etc.

• Understanding of memory controller architecture, memory scheduling, prioritization and QoS

• Understanding memory PHY parameters and tradeoffs, including for LPDDR, DDR, and HBM

• Fluid knowledge of one or more JEDEC standards such as LPDDR, DDR, or HBM, and the ability to analyze such standards and drive recommendations

• Experience working with or working at the major DRAM and other memory vendors

• Background in memory systems and computer architecture to understand the tradeoffs among memory bandwidth, latency, performance, power, SoC area

• Understanding memory technology parameters such as reliability, thermals, ECC, encryption, etc.

• PHY shoreline, packaging, stacking, etc.

• Excellent communication, documentation, and interpersonal skills with ability to convey proposals and interact effectively across a distributed multi-discipline organization

• Ability to abstract appropriately to define problems and solution, and make data-drive decisions

• Record of quantitative analysis using (and developing) tools such as high-level calculators & spreadsheets, DRAM timing simulators, profilers, functional and performance simulators, etc.

• Experience driving JEDEC or similar standardization is a plus

Minimum Qualifications:

• MS or PhD degree in EE/ECE/CE/CS or related field required

• 10+ years of experience in memory architecture, memory technology, and computer architecture

Additional Experience and Expertise:

• Memory technologist expertise, such as the internal cell structure for DRAM, MRAM, NAND Flash, etc.

• Generative AI & Machine Learning workloads

• SoC architecture including heterogeneous compute, NoC/interconnect, multicore, multi-die, cache hierarchies, shared memory, I/O, coherency, compression, security, etc.

• Safety, reliability, security, and high-resilience/high-availability systems

• External memory and storage architectures (e.g., CXL, PCI, NVMe, etc.)

• Analytical modeling for performance, power, area, cost, etc.

• Behavioral, functional and performance modeling

• Power and/or performance optimization through simulation & modeling

• Simulator architectures and frameworks (C++ or Python-based preferred)

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range:

$198,000.00 - $340,000.00