Intel Physical Design Methodology Engineer 

India, Karnataka, Bengaluru 

946638224

Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the physical design implementation of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Establishes regression flows, drives improvement in RTL to GDS flows, and creates and implements methodologies for improving robustness, power, performance, area, and timing for optimizing physical design constraints. Develops new physical design techniques through innovative scripts, checkers, flows, and other CAD based automation to simplify and expedite the design process. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transformative changes to the existing physical design-related TFM. Partners with physical design, circuits, CAD, RTL, tool/flow owners, and EDA vendor teams to continuously improve physical design methodologies and efficiencies.

Degree(BS/MS) in electronics engineering

Experience: 1.5 to 3.5 years

• Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies like concepts related to synthesis, place and route, CTS, timing convergence, layout closure. Expertise on high frequency design methodologies.
• Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification.
• Working experience with tools like ICC/ICC2,Fusion Compiler Primetime , Innovus etc. used in the RTL2GDSII implementation
• Strong knowledge and experience in standard place and route flows ICC2/FusionCompiler Synopsys flows preferred.
• Well versed with timing constraints, STA and timing closure.
• Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place and Route too.
• Ability to multi-task and flexibility to work in global environment.
• Good communication skills and strong motivation for customer support. Strong analytical and Problem solving skills.