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Google ASIC Design Testability Engineer Lead Silicon 
India, Karnataka, Bengaluru 
935375249

12.06.2024
Minimum qualifications:
  • Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, or equivalent practical experience.
  • 3 years of experience in design for testability.
  • Experience with ATPG, LV, built-in self test (BIST), Joint Test Action Group (JTAG) tools and flow.

Preferred qualifications:
  • Experience with a scripting language (e.g., Perl) and with Synthesis, Logic Testing, and ATPG.
  • Ability to scale design for testing (DFT).