Microsoft DFD Design Debug RTL Execution Lead 

Taiwan, Taoyuan City 

926820764

Required/minimum qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
• 7+ years of experience in Computer Architecture, Digital Design, CPU/SoC design and verification principles as part of CPU, SoC and/or IP development.

Other Qualifications:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Additional Preferred Qualifications

• Expert in designing debug IP’s & SOC integration. Includes building and integrating any of the Debug IPs such as the ones provided by ARM Coresight.
• Highly Proficiency in System Verilog & scripting along with excellent knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting).
• Understanding in clock crossing techniques & UPF (Low power intent).
• Previous experience working on post-silicon debug / validation, especially during power ON & FA/FI.
• Hands on contribution towards Debug Architecture along with good knowledge of Industry standard standards.
• Proactive & self-motivated, eager to learn and contribute in a team environment, committed and accountable. Confident problem solver who thrives under pressure to find new, creative solutions.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until July 28th, 2025.

• Define the micro-architectural implementation spec for debug IP’s, fabrics & implement the micro-architectural specification in Verilog or System Verilog.
• Lead a team of engineers for IP & product DFD deliverables and support individual contributors in their own career growth.
• Work as part of DFX (Test & Debug) team & closely collaborate with highly energetic cross functional team members (system architects, front-end & back-end design verification, and post-si validation folks) with respect and with One Microsoft mentality to establish synergies.
• Refine Debug execution methodology and use of industry/home-grown tools to ensure design quality, effectiveness & speed up execution.
• Hold a primary role in enabling silicon by working directly with validation & fleet engineers to bring up debug capabilities and to help with diagnostics & screening.
• Work closely on Debug tool POC & roadmap associated with the RTL features implemented in design.
• Assess and then refine the implementation for debug coverage, area, power and performance. Ensure quality with checks covering Lint, CDC, Low Power intent and more.
• Delight your customers by delivering cutting-edge debug IP’s & infrastructure for custom SoC designs that can perform complex and high-performance functions. Challenge the status quo with growth mindset.