Intel SoC Design Verification Engineer United States, Texas 922231005
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As aSoC Design Verification Engineer, your responsibilities will include but are not limited to:
Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
Executes verification plans and defines and runs system simulation models to verify the design, analyze power and performance, and uncover bugs.
Replicates, root causes, and debugs issues in the pre-silicon environment.
Finds and implements corrective measures to resolve failing tests.
Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
Maintains and improves existing functional verification infrastructure and methodology.
Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products.
Behavioral traits that we are looking for:
Robust understanding of fundamental principles of SOCs, Chipset architecture.
Experience with one or more scripting languages to facilitate automation.
Strong debug skills and self-reliance in taking an issue to closure with internal and external partners. Takes ownership of assigned tasks.
Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market
for more details.
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum skills and experience that will get you noticed:
Bachelor's Degree in Degree in Electrical engineering or Computer engineering and 4+ years of experience -OR- Master's Degree with 3+ years of experience
Candidate must have experience in at least 2 of the following:
·Computer architecture,
·System Verilog, OVM/UVM
·SOC-level design integration and or validation,
·simulation-based debug
Preferred skills and experience that will make you stand out:
Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.
Proficiency in UVM/SV constrained-random coverage-based design verification.
OVM/UVM, System Verilog, constrained random verification methodologies.
Complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).
Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.
UVM/SV Verification architecture, development and validation experience.
Experience in SOC Pre-Silicon Validation.
Position of Trust
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
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