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Apple FE Implementation Engineer United Kingdom, England, London 908949644
06.06.2024
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Key Qualifications
- Experience with physical synthesis, including logic and PPA optimisation techniques.
- Understanding and application of physical design and static timing analysis principles.
- Proficient in Verilog and/or System Verilog and scripting languages.
- Ability to analyze critical paths and guide RTL designs to efficient solutions.
- Experience using logic equivalence tools for RTL and Gate-level designs.
- Collaborate optimally with IP teams spanning multiple sites.
- Additional Qualifications - Preferred, but not required:
- Familiarity with DFT insertion;
- Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level;
- Experience implementing ECOs for functionality and timing.
Education & Experience
Minimum of BSc in EE.
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