Nvidia Senior Physical Design Engineer 

United States, California 

883179478

We are actively looking for Physical design Engineers with RTL2GDS experience to implement complex high performance and low power SOC’s.

What you'll be doing:

• Responsible to Floor Planning and Place and route (P&R) of High-performance chip partitions.

• Integration on Analog IO’s and macros.

• Work on power grid planning, Clock tree Synthesis (CTS) and timing closure.

• Multi mode and multi corner timing closure, RC extraction, Cross talk, IR drop and EM analysis.

• Work with the Front-end teams to update and tune timing constraints.

• Debugging timing violations and rolling in functional, Timing ECO’s and netlist formal verification.

• Physical verification- ERC, DRC, LVS etc.

What we need to see:

• Bachelor's or a Master’s degree in Engineering or equivalent experience.

• 6+ years of hands-on experience in Physical design.

• Place and route tool experience with Synopsys ICC2 or Candence Innovus

• Static timing analysis with Synopsys Primetime.

• Understanding of DFT and multi-mode timing analysis.

• Ability to automate flows.