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What you'll be doing:
As a member in our team, you will help develop and deploy DFT verification methodologies for various DFT features in our next generation products.
Help define and develop tesplans, testbenches and checkers based on review of functional description of DFT designs.
Develop or modify full chip verification infrastructure based on advanced verification methodologies.
Support emulation sign off of DFT features by collaborating with cross functional teams and also actively support post silicon bring up
You will also help mentor junior engineers on test designs and trade-offs including cost and quality.
What we need to see:
BSEE (or equivalent experience) with 5+, MSEE with 3+ years of experience or PhD in DFT or related domains
Experience in developing robust test plans and building verification infrastructure for pre-si validation and post-si bring up.
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation
Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
Strong programming and scripting skills in Perl, Python or Tcl desired
Extraordinary written and oral communication skills with the curiosity to work on rare challenges
You will also be eligible for equity and .
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