Broadcom Serdes / High Speed IO DFT engineer 

United States, Colorado, Fort Collins 

881479625

SerDes DFT & Test Engineer

Key Responsibilities:

• Implement and verify DFT methodologies for SerDes IP.

• Collaborate with design and architecture teams to identify and define critical testability requirements.

• Utilize advanced simulation tools and methodologies to thoroughly verify DFT implementations.

• Analyze DFT-related data and provide insights for continuous design improvements.

• Document verification processes, results, and best practices to enhance team knowledge and efficiency.

• Stay updated with the latest trends and technologies in DFT to drive innovation within the team.

• Working closely with STA and DI Engineers design closure for the test.

• Generating, Verifying & Debugging Test vectors before tape release.

• Validating & Debugging Test vectors on ATE during the silicon bring up phase.

• Assisting with silicon failure analysis, diagnostics & yield improvement efforts.

• Interfacing with the customers, physical design and testengineering/manufacturingteams spanning multiple geographies.

• Working closely with I/P DFT engineers & other stakeholders.

• Debugging customers returned parts on the ATE.

• Automating DFT & Test Vector Generation flows

Skills/Experience:

• Good understanding of Mixed Signal IPs, Digital and Analog logic.

• Strong DFT background (such as Analog DFT, MBIST, IEEE1687 and others)

• Proven experience in DFT verification with detailed understanding of Serdes IP architecture, specifications.

• Understanding of DFT methodologies, including scan, BIST, and ATPG.

• Proficiency in simulation tools and scripting languages (e.g., Perl, Python, TCL and ruby).

• Strong communication and teamwork abilities.

• The ability to work in a multi-disciplined, cross-functional worldwide team environment.

• Solid knowledge in analog and digital circuit design, and device physics fundamentals.

• Excellent problem solving, debug , root cause analysis and communication skills.

• Experience working on ATE is a plus.

• Familiarity with BIST logic for array and link testing.

• Knowledge of AHB/APB/AXI buses & Protocols such as PCIe, JESD, Ethernet are a plus.
  

Education & Experience:

• Bachelors inElectrical/Electronic/ComputerEngineering and 15+ years of relevant industry experience or Masters Degree inElectrical/Electronic/ComputerEngineering and 13+ years of relevant industry experience

Compensation and Benefits

The annual base salary range for this position is $146,000 - $234,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.