Samsung DFX Engineer 

United States, Texas, Austin 

875869076

Role and Responsibilities

As a seasoned DFX engineer, you will be involved across the entire spectrum of activities all the way from defining the DFT scan architecture through implementation and culminating in pattern generation including silicon debug. You will be working on IP-level projects (GPU, system interconnect) in bleeding-edge processes that continually drive high test-coverage requirements.

Your specific responsibilities will include:

• You understand SOC requirements and project milestones to help define a DFT architecture which optimally balances between coverage, test-time, andexecution.
• You create a detailed implementation spec which documents details of the architecture including SOC-level interface, clock design, and support of various test/debug modes.
• You close on the spec with stakeholders including DFX / RTL / SOC / STA / PD teams.
• You implement DFT scan: RTL creation, LINT, timing-constraints, ATPG andsimulation.Benchmark test-coverage and test-time to ensure that they meetexpectations.
• You drive towards continuing DFX excellence: improving test-coverage, minimizing test-time, and exploring tools / methods that improve execution efficiency.
• You build strong collaboration with SOC and Product/Test Engineering teams to quickly resolve any silicon issues including test-escapes and yield loss.

Skills and Qualifications

• 10+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master’s degree, or 6+ years of experience with a PhD
• 10+ years of DFX expertise encompassing multiple tapeouts for digital IP (CPU / GPU) and/or SOC projects
• Demonstrated ability to architect DFT solutions from scratch on at least 1 project, and to create detailed specifications that can be used as a blueprint for implementation.
• Detailed understanding of test-coverage requirements across various scan modes especially as they pertain to bleeding-edge process nodes.
• Strong familiarity with RTL coding & STA with working knowledge of Physical Design
• Familiarity with multi-voltage and multi-clocking domain implementation is a plus.
• Exposure to advanced approaches including hierarchical DFT and streaming fabric.
• Strong post-silicon experience as it relates to debugging silicon behavior and test-escape issues. Is able to solve difficult problems with creative solutions or analysis.
• Crisp written and oral communication skills including working with global stakeholders
• Thrives in fast-paced environment: i.e. yearly project tapeouts

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.