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Apple Timing Engineer F Germany, Bavaria, Munich 870135125
28.03.2024
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Key Qualifications
- - Basic knowledge of the VLSI design timing closure flow and methodology.
- - Experience in STA methodologies for timing closure, and have a basic understanding of noise, cross-talk, and OCV effects, among others.
- - Basic experience with scripting languages (TCL & Perl).
- - Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools - An advantage.
- - Background in Constraint analysis and debug, using industry standard tools as well as backend STA closure - An advantage.
- - Experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing - An advantage.
- - A team player that collaborate well with peers.
- - Ability to fluently speak and write in English.
Description
Responsibilities include especially, but are not limited to:- Work with Physical Design team, highlighting issues and best practices.- Help build timing ECO’s for project tapeout.- Build/maintain scripts and methodologies for analysis and runs.You will be responsible for constraints and timing checkups development, including their delivery for synthesis, PnR and signoff STA. Working in parallel on blocks and chip level STA modes.
Education & Experience
Bachelors's or Master's Degree in a technical field is required.
Additional Requirements
- Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. Apple is a drug-free workplace
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