As a member of our CAD team, you will develop, maintain, and enhance existing parasitics extraction flow for Apple’s successful silicon designs. You will use the most efficient RC analysis skills on various designs to diagnose and debug parasitic effects and guide and design improvement for balanced and minimized parasitic impact. Your experience and proficient usage of EDA extraction tools and methodologies will ensure parasitic RLC accuracy and circuit performance in post-layout simulations. You must deeply understand parasitic modeling in advanced process technologies and use the knowledge to explain circuit behavior and performance. You will work closely with EDA vendors to incorporate new capabilities to solve technical problems. You can develop an RC-aware or RC-driven methodology for design optimization.