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Available Job Responsibilities
Analyze different memory architectures and highlight the tradeoffs
Design and build memory or circuit blocks at the gate or transistor level
Simulate and analyze the circuit design using transistor level simulators
Extract the layout and perform post-layout simulations and verification
Floorplan physical implementation and leafcell layout integration to build the physical macro
Integrate characterization flow to extract timing and power information
Develop scripts to automate characterization flow, simulations, and verification
Specify and verify various behavioral and physical memory models
Document the design specifications, behavioral description, and timing diagrams
Specify silicon test plan and correlate silicon to simulation data
Help debug silicon issues
Skillset Required
Strong Expertise in development of memory compilers and custom macros of all types; SRAMs, Register-files, Multi-ports, ROM, etc…
Deep understanding of transistor level circuit behavior and device physics
Deep understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
Good understanding of memory behavioral and physical models
Good understanding of DFT schemes and chip level integration
Familiar with test setups, silicon testing and debug
Proficient in running simulators, writing automation scripts, and are tools savvy
Good communication, interpersonal, and leadership skills
Motivated, self-driven and good at multi-tasking
Qualifications
Requires a BS in Electrical or Computer Engineering and 12+ years of related experience
Compensation and Benefits
The annual base salary range for this position is $127,000 - $203,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
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