Finding the best job has never been easier
Share
Who You Are
As a member of our team, you will play a key role in developing PCIe gen7 IP from architectural specifications to a fully capable design that will meet area, power, performance, and timing requirements.
You will be responsible for, but not limited to:
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Candidate must have a Bachelor's Degree in Electrical Engineering or Computer Engineering with 4+ years of industry experience -OR- Master's Degree in Electrical Engineering or Computer Engineering with 3+ years of industry experience -OR- PhD in Electrical Engineering and/or Computer Engineering.
Experience in Verilog, System Verilog
Experience in Logic Design, RTL Design
Knowledge of Design Tools and Design Analysis such as Design Compiler, CDC (Clock Domain Crossing), Closing Timing Violations
Preferred Qualifications
Scripting experience in languages like Python, Perl etc
Experience in Power Management IP, Power Management SoC, DFX knowledge
Experience in Verification Tools
offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
These jobs might be a good fit