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What you'll be doing:
In this highly technical role, you will work on end-to-end DFT for the most sophisticated chips in the world, from methodology, to deployment to post-silicon lifecycle support.
Partner with the top EDA tool vendors to develop new capabilities to support NVIDIA requirements, and with internal CAD to drive efficiency via automations.
Work with NVIDIA VLSI and Operations teams to deliver the scan feature in all product segments at NVIDIA.
Help mentor junior engineers on test designs and trade-offs including cost and quality.
What we need to see:
Pursuing a BSEE or MSEE (or equivalent experience).
Knowledge in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation.
Excellent analytical skills in verification and validation of test patterns and logic on sophisticated and multi-million gate designs using vendor tools.
Good exposure to multiple domains including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs.
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.
Ways to stand out from the crowd:
Strong programming and scripting skills in Perl, Python or Tcl desired.
You will also be eligible for equity and .
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