Your responsibilities will include but not be limited to:
Validation of an IP or feature at the SoC level
Creating plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide
Learning the architecture and microarchitecture by debugging failures to the root cause
Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design
Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models
Minimum Qualifications:
Must have either a BS/Btech +6 years' experience or MS/MTech + 4 years' experience in Computer Science, Computer Engineering or Electrical Engineering.
Minimum 3 years’ experience working on Validation, verification, or integration usingVerilog/System Verilog
Minimum 3 years’ experience with writing validation plans and software to implement those validation plans
Minimum 3 years’ experience with an object-oriented programming language
Minimum 3 years’ experience with Verilog or other HDL